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1. 发明专利

JP2009283800A Semiconductor integrated circuit and electronic circuit device 有权
标题翻译：半导体集成电路和电子电路设备
公开(公告)号：JP2009283800A
公开(公告)日：2009-12-03
申请号：JP2008136203
申请日：2008-05-26
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： DOBASHI HIROYUKI , YAMADA JUNJI , AOKI KENICHI , UEMOTO AKIRA
IPC分类号： H01L21/822 , B41J2/44 , B41J2/45 , B41J2/455 , H01L21/8234 , H01L27/04 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To suppress changes in the electrical characteristics of an MOS transistor, in a semiconductor integrated circuit due to stress, when it is exerted in the semiconductor integrated circuit.
SOLUTION: Gate electrodes 13A of an output MOS transistor 1T are extended in a long side direction D1 of a semiconductor substrate 10 (that is, in a direction which is parallel to the long side). A source region, and a drain region (both not illustrated) are provided on both sides of the gate electrode 13A, and a channel region (not shown) is formed therebetween. Also for each control MOS transistor (not shown) included in each control circuit 1L, gate electrodes 13B may be extended in the direction of the long side D1 of the semiconductor substrate 10.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：当在半导体集成电路中施加时，抑制由于应力而导致的半导体集成电路中的MOS晶体管的电特性的变化。解决方案：输出MOS晶体管1T的栅电极13A在半导体衬底10的长边方向D1（即，与长边平行的方向上）延伸。源极区域和漏极区域（均未示出）设置在栅电极13A的两侧，并且在其间形成沟道区域（未示出）。对于每个控制电路1L中包括的每个控制MOS晶体管（未示出），也可以在半导体衬底10的长边D1的方向上延伸栅极13B。（C）2010，JPO＆INPIT

2. 发明专利

JP2009218503A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009218503A
公开(公告)日：2009-09-24
申请号：JP2008063091
申请日：2008-03-12
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： DOBASHI HIROYUKI , SHIKANUMA YOICHI , YAMADA JUNJI , SAITO KIMIHIDE
IPC分类号： H01L21/768 , H01L21/301 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To improve reliability by suppressing the penetration of cracks from a sidewall of a semiconductor chip in dicing.
SOLUTION: On the edge of the surface of a semiconductor chip region 10, a planarization insulation film region 30 is formed while surrounding an integrated circuit region 31. The planarization insulation film region 30 is formed by replacing a portion where a conventional dummy metal layer has been formed with a dummy insulation film. On a first interlayer insulating film 12 extended from the integrated circuit region 31, three dummy insulation film patterns 20 are formed at a fixed interval. Also, a second interlayer insulating film 14 extended from the integrated circuit region 31 covers the three dummy insulation film patterns 20, and three dummy insulation film patterns 21 are formed at a fixed interval also in the second interlayer insulation film 14. Furthermore, a third interlayer insulation film 16 extended from the integrated circuit region 31 covers the three dummy insulation film patterns 21, and three dummy insulation film patterns 22 are formed at a fixed interval also in the third interlayer insulation film 16.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在切割中抑制来自半导体芯片的侧壁的裂纹的渗透来提高可靠性。解决方案：在半导体芯片区域10的表面的边缘处，形成平坦化绝缘膜区域30，同时围绕集成电路区域31。平坦化绝缘膜区域30通过替换传统虚拟器件金属层已经形成有虚拟绝缘膜。在从集成电路区域31延伸的第一层间绝缘膜12上，以固定间隔形成三个虚拟绝缘膜图案20。此外，从集成电路区域31延伸的第二层间绝缘膜14覆盖三个虚拟绝缘膜图案20，并且在第二层间绝缘膜14中也以固定间隔形成三个虚拟绝缘膜图案21.此外，第三层从集成电路区域31延伸的层间绝缘膜16覆盖三个虚拟绝缘膜图案21，并且在第三层间绝缘膜16中以固定间隔形成三个虚拟绝缘膜图案22.（C） 2009年，JPO＆INPIT

3. 发明专利

JP2009218504A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009218504A
公开(公告)日：2009-09-24
申请号：JP2008063092
申请日：2008-03-12
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： DOBASHI HIROYUKI , SHIKANUMA YOICHI , YAMADA JUNJI , UEMOTO AKIRA , SAITO KIMIHIDE
IPC分类号： H01L21/3205 , H01L21/301 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To improve reliability by suppressing the penetration of cracks from a sidewall of a semiconductor chip in dicing.
SOLUTION: On an edge of the surface of a semiconductor chip region 10, a sealing ring 30 for crack stoppers is formed while surrounding an integrated circuit region 31. In the sealing ring 30 for crack stoppers, namely a laminated structure formed on a semiconductor substrate 11 outside the integrated circuit region 31, first, second, and third dummy metal layers 20, 21, 22 are laminated while sandwiching first, second, and third interlayer insulating films 12, 14, 16, respectively. The first, second, and third dummy metal layers 20, 21, 22 are electrically insulated from the semiconductor element and wiring of the integrated circuit region 31 by the first to third interlayer insulating films 12, 14, 16.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在切割中抑制来自半导体芯片的侧壁的裂纹的渗透来提高可靠性。解决方案：在半导体芯片区域10的表面的边缘上，形成用于防止裂缝的密封环30，同时围绕集成电路区域31.在用于裂缝阻挡物的密封环30中，即形成在在集成电路区域31的外侧的半导体衬底11，分别夹着第一，第二和第三层间绝缘膜12,16的层叠第一，第二和第三虚设金属层20,21,22。第一，第二和第三虚设金属层20,21,22通过第一至第三层间绝缘膜12,14,16与半导体元件和集成电路区域31的布线电绝缘。（版权所有： C）2009年，JPO＆INPIT

4. 发明专利

JP2005159336A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005159336A
公开(公告)日：2005-06-16
申请号：JP2004314629
申请日：2004-10-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： IIZUKA KATSUHIKO , OKADA KAZUHISA , MORI TOMONORI , DOBASHI HIROYUKI , HONDA TAKAYOSHI , SUZUKI HIROYUKI , TANIGUCHI TOSHIMITSU
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To form an LDD structure and a salicide region, without causing generation of scraping of a silicon substrate or carbon contamination.
SOLUTION: When a spacer 6 is formed on the side surface of a gate electrode 3, etching of an insulating film 5 is performed, by dividing the etching into two steps of dry etching and wet etching. Moreover, a silicon nitride film is used as a buffer film in the case of high concentration impurity injection, and removing of this film is performed by wet etching. As a result, scraping of the silicon substrate 1 and carbon contamination can be prevented. Further, the depth of the impurity region and a silicide formation region and in-plane variations of resistance become small from the high state of selection ratio which is a feature of wet etching.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了形成LDD结构和自对准硅化物区域，不会产生刮擦硅衬底或碳污染物。解决方案：当在栅电极3的侧表面上形成间隔物6时，通过将蚀刻分为干法蚀刻和湿蚀刻两个步骤来进行绝缘膜5的蚀刻。此外，在高浓度杂质注入的情况下，使用氮化硅膜作为缓冲膜，并且通过湿蚀刻进行该膜的去除。结果，可以防止硅衬底1的刮擦和碳污染。此外，杂质区域和硅化物形成区域的深度以及电阻的面内变化从作为湿蚀刻特征的高选择率状态变小。版权所有（C）2005，JPO＆NCIPI

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