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1. 发明专利

JP2006270382A Level shifting circuit and power supply device 有权
标题翻译：水平移动电路和电源设备
公开(公告)号：JP2006270382A
公开(公告)日：2006-10-05
申请号：JP2005084132
申请日：2005-03-23
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： IWABUCHI AKIO , TAKAHASHI TETSUYA
IPC分类号： H03K17/04 , H02M7/538 , H03K17/687
CPC分类号： H03K19/018507 , H02M7/538 , H03K17/063
摘要： PROBLEM TO BE SOLVED: To provide a level shifting circuit restraining a power consumption by using a simple circuit configuration and being capable of realizing a high-speed operation and a power supply device. SOLUTION: The level shifting circuit 3 has an inverter circuit 9 constituted of the series circuit of a Pch type transistor Q11 and an Nch type transistor Q12 connected between electrodes for a floating power supply BSD and the transistor Q1 in which a drain terminal and a source terminal are connected between an input terminal for the inverter circuit 9 and a ground. In the level shifting circuit 3, the drain terminal and the source terminal for the transistor Q2 are connected between one terminal for the floating power supply BSD and a drain for the transistor Q1, and the drain terminal and the source terminal for the transistor Q3 are connected between a control terminal for the transistor Q2 and the ground. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过使用简单的电路配置并且能够实现高速操作和电源装置来限制功耗的电平转换电路。电平移位电路3具有由Pch型晶体管Q11和Nch型晶体管Q12的串联电路构成的反相电路9，该串联电路连接在浮置电源BSD的电极和漏极端子并且源极端子连接在用于逆变器电路9的输入端子和地之间。在电平移位电路3中，用于晶体管Q2的漏极端子和源极端子连接在用于浮动电源BSD的一个端子和晶体管Q1的漏极之间，漏极端子和晶体管Q3的源极端子连接在晶体管Q2的控制端和地之间。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2005026262A Bidirectional thyristor 有权
标题翻译：双向THYRISTOR
公开(公告)号：JP2005026262A
公开(公告)日：2005-01-27
申请号：JP2003186861
申请日：2003-06-30
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： KAMIMURA TATSUYA , TAKAHASHI TETSUYA
IPC分类号： H01L29/747
摘要： PROBLEM TO BE SOLVED: To provide a bidirectional thyristor that can be improved in sensitivity and can be prevented from making malfunctions.
SOLUTION: In order to constitute the bidirectional thyristor, first, second, third, and fourth n-type semiconductor regions N1, N2, N3, and N4, and first and second p-type semiconductor regions P1 and P2, are provided in a semiconductor substrate 1. Then a first main electrode T1 and a gate electrode G1 are disposed on one principal surface 2 of the substrate 1, and a second main electrode T2 is provided on the other principal surface 3 of the substrate. In addition, a gate trigger current suppressor 10 composed of an n-type semiconductor is provided from the first n-type semiconductor region N1 to the surface 2 of the semiconductor substrate 1. The gate trigger current suppressor 10 is disposed between the portion of the first main electrode T1 disposed above the third n-type semiconductor region N3 and the gate electrode G in the top view of the thyristor.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以提高灵敏度并且可以防止发生故障的双向晶闸管。解决方案：为了构成双向晶闸管，提供了第一，第二，第三和第四n型半导体区域N1，N2，N3和N4以及第一和第二p型半导体区域P1和P2 然后在基板1的一个主表面2上设置第一主电极T1和栅电极G1，在基板的另一个主表面3上设置第二主电极T2。此外，从第一n型半导体区域N1到半导体衬底1的表面2设置由n型半导体构成的栅极触发电流抑制器10.栅极触发电流抑制器10设置在设置在第三n型半导体区域N3上方的第一主电极T1和晶闸管的俯视图中的栅极电极G. 版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2007012786A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007012786A
公开(公告)日：2007-01-18
申请号：JP2005190048
申请日：2005-06-29
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： TAKAHASHI TETSUYA
IPC分类号： H01L21/336 , H01L27/04 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing recovery time (reverse recovery time) without increasing operation resistance upon operation of an element. SOLUTION: The semiconductor device comprises first and second trenches 103, 104 formed to face each other on a first conductivity type semiconductor substrate 100 via a first conductivity type first semiconductor region 102 formed on the semiconductor substrate, a gate insulating film 105 formed on the side surfaces of the first and second trenches, a gate electrode 106 formed inside the first and second trenches, a second conductivity type second semiconductor region 107 formed to make contact with the first semiconductor region, a first conductivity type third semiconductor region 108 in contact with the second semiconductor region, and further a life time control region 110 formed in the first semiconductor region between the first and second trenches facing each other. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在元件操作时不增加操作阻力的同时减少恢复时间（反向恢复时间）的半导体器件。解决方案：半导体器件包括通过形成在半导体衬底上的第一导电类型的第一半导体区域102在第一导电类型半导体衬底100上彼此面对形成的第一沟槽103和第二沟槽104，形成的栅极绝缘膜105 在第一沟槽和第二沟槽的侧表面上形成有形成在第一和第二沟槽内的栅电极106，形成为与第一半导体区域接触的第二导电类型的第二半导体区域107，第一导电类型的第三半导体区域108 与第二半导体区域接触，并且还在第一和第二沟槽之间的第一半导体区域中形成的寿命控制区域110彼此面对。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006319218A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006319218A
公开(公告)日：2006-11-24
申请号：JP2005141885
申请日：2005-05-13
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： TAKAHASHI TETSUYA
IPC分类号： H01L29/739 , H01L21/76 , H01L29/06 , H01L29/749 , H01L29/78
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/0696 , H01L29/407
摘要： PROBLEM TO BE SOLVED: To improve the resistance properties of a pn junction in a semiconductor device such as IGBT. SOLUTION: A trench 17 is provided on the circumference of an IGBT semiconductor substrate 1 equipped with a p + type collector area 8, an n - type base area 9, a p + type base area 10 and an n + type emitter area 11. This trench 17 is formed in a way that it penetrates into the p + type collector area 8 through the n - type base area. A conductor layer 24 is provided on the wall of the trench 17 in a way that it is not only opposed to the side of the n - type base area 8 via the dielectric film 23, but also it is connected to the p + type collector area 8. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高诸如IGBT的半导体器件中的pn结的电阻特性。解决方案：沟槽17设置在配备有p + 型集电极区域8，n - / SP>型基极区域9的IGBT半导体衬底1的圆周上， ap + 型基础区域10和n + 型发射器区域11.该沟槽17形成为穿透p + 类型集合区8通过n - 类型基区。在沟槽17的壁上设置导体层24，其不仅通过电介质膜23与n - SP型基底区域8的一侧相对，而且它也是连接到p + 类型收集器区域8.版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2004214397A Composite type semiconductor device and method for manufacturing the same 有权
标题翻译：复合型半导体器件及其制造方法
公开(公告)号：JP2004214397A
公开(公告)日：2004-07-29
申请号：JP2002381887
申请日：2002-12-27
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： KOSUGI KIMIAKI , TAKAHASHI TETSUYA
IPC分类号： H01L29/74 , H01L21/332 , H01L29/866
摘要： PROBLEM TO BE SOLVED: To provide a composite type semiconductor element where voltage to be turned on is easily set to a desired value.
SOLUTION: The composite type semiconductor element is provided with a thyristor consisting of an n1 area 11, a p1 area 12, an n2 area 13 and a p2 area 14, a first diode consisting of a first p-type semiconductor area 15 and a first n-type semiconductor area 16 and connected to the p1 area, and a second diode consisting of a second p-type semiconductor area 17 and a second n-type semiconductor area 18 and connected to the n1 area. The first and second diodes are connected in series so that the flowing direction of currents flowing through each by breakdown. By properly increasing the number of diodes to be connected, it is possible to make the thyristor turn on a desired high voltage.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种复合型半导体元件，其中要接通的电压容易设定为期望值。解决方案：复合型半导体元件设置有由n1区域11，p1区域12，n2区域13和p2区域14组成的晶闸管，由第一p型半导体区域15 以及与p1区域连接的第一n型半导体区域16，以及与n1区域连接的由第二p型半导体区域17和第二n型半导体区域18构成的第二二极管。第一和第二二极管串联连接，使电流的流动方向通过击穿而流过。通过适当地增加要连接的二极管的数量，可以使晶闸管导通期望的高电压。版权所有（C）2004，JPO＆NCIPI

6. 发明专利

JP2007059766A Trench structure semiconductor device and its manufacturing method 有权
标题翻译： TRENCH STRUCTURE SEMICONDUCTOR DEVICE及其制造方法
公开(公告)号：JP2007059766A
公开(公告)日：2007-03-08
申请号：JP2005245533
申请日：2005-08-26
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： TAKAHASHI TETSUYA
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/404 , H01L29/407
摘要： PROBLEM TO BE SOLVED: To permit easy achievement of breakdown voltage improvement of pn junction for a trench structure semiconductor device for IGBT (insulated gate bipolar transistor) or the like.
SOLUTION: A semiconductor substrate 1 is provided with a plurality of first trenches 5 for constituting a cell for the IGBT at the center 4, and a plurality of second trenches 7 for improving breakdown voltage at the outer periphery 6. A first insulating film 18 and a first trench conductor 19 are arranged in the first trench 5, while a second insulating film 26 and a second trench conductor 27 are arranged in the second trench 7. A plurality of capacity coupling conductor layers 29 are provided to effect capacity coupling between mutual second trench conductors 27.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了容易地实现用于IGBT（绝缘栅双极晶体管）等的沟槽结构半导体器件的pn结的击穿电压的改善。解决方案：半导体衬底1设置有用于构成中心4处的IGBT的单元的多个第一沟槽5和用于改善外周6处的击穿电压的多个第二沟槽7.第一绝缘膜18和第一沟槽导体19布置在第一沟槽5中，而第二绝缘膜26和第二沟槽导体27布置在第二沟槽7中。提供多个电容耦合导体层29以实现电容耦合在相互的第二沟槽导体27之间。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2007019289A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007019289A
公开(公告)日：2007-01-25
申请号：JP2005199758
申请日：2005-07-08
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： TAKAHASHI TETSUYA
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/407 , H01L29/0653 , H01L29/0878 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a high breakdown voltage.
SOLUTION: This semiconductor device 10 comprises an n-type diffusion layer 17 between an insulating layer 15 formed on the surface of a trench 19 and an n-type semiconductor region 11. An n-type impurity is diffused into the n-type diffusion layer 17 with a concentration gradient provided in the direction connecting a source electrode 21 and a drain electrode 22. By providing the n-type diffusion layer 17, a depletion layer is well generated in the semiconductor device 10 when a reverse voltage is applied, and a leakage current can also be decreased, so that the semiconductor device 10 will have a high breakdown voltage.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供具有高击穿电压的半导体器件。解决方案：该半导体器件10包括在形成在沟槽19的表面上的绝缘层15和n型半导体区域11之间的n型扩散层17.n型杂质扩散到n- 型扩散层17，其具有在连接源电极21和漏电极22的方向上提供的浓度梯度。通过提供n型扩散层17，当施加反向电压时，在半导体器件10中良好地产生耗尽层并且也可以减小漏电流，使得半导体器件10将具有高的击穿电压。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006303111A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006303111A
公开(公告)日：2006-11-02
申请号：JP2005121434
申请日：2005-04-19
申请人： Sanken Electric Co Ltd , サンケン電気株式会社
发明人： TAKAHASHI TETSUYA
IPC分类号： H01L29/861 , H01L29/786
CPC分类号： H01L29/861 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/7394 , H01L29/7824 , H01L29/78624 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element which obtains a high withstanding voltage property without changing the impurity concentration or the size of the semiconductor element.
SOLUTION: The semiconductor element 10 comprises a semiconductor substrate 20, an anode electrode 17 and a cathode electrode 18. The semiconductor substrate 20 has a p-type semiconductor substrate 11, an insulation film 12, an n
- -type semiconductor region 13 formed on the film 12, an n
+ -type semiconductor region 14, and a p
+ -type semiconductor region 15 opposite to the n
+ -type semiconductor region 14 through the n
- -type semiconductor region 13. The semiconductor element 10 comprises an n-type diffusion layer 16 formed in the n
- -type semiconductor region 13 at the interface between the insulation layer 12 and the semiconductor region 13 with an n-type impurity concentration gradient increasing from the anode electrode 17 toward the cathode electrode 18.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在不改变半导体元件的杂质浓度或尺寸的情况下获得高耐压性的半导体元件。解决方案：半导体元件10包括半导体衬底20，阳极电极17和阴极电极18.半导体衬底20具有p型半导体衬底11，绝缘膜12，n < / SP>型半导体区域13，n + SP +型半导体区域13，n + SP> + 型半导体区域14。半导体元件10包括形成在n 型半导体区域13中的n型扩散层16。 / SP>型半导体区域13，其中绝缘层12和半导体区域13之间的界面具有从阳极电极17朝向阴极电极18增加的n型杂质浓度梯度。版权所有（C）2007 ，JPO＆INPIT

9. 发明专利

JP2003142595A TRANSISTOR 审中-公开
公开(公告)号：JP2003142595A
公开(公告)日：2003-05-16
申请号：JP2001342269
申请日：2001-11-07
申请人： SANKEN ELECTRIC CO LTD
发明人： KONO YOSHINOBU , TAKAHASHI TETSUYA
IPC分类号： H01L21/331 , H01L21/82 , H01L21/8222 , H01L27/082 , H01L29/70 , H01L29/732
摘要： PROBLEM TO BE SOLVED: To provide a switching transistor capable of performing a high-speed switching operation. SOLUTION: P type 1st, 2nd and 3rd base areas 18 to 20 are formed on an N type collector area 15. N type 1st, 2nd and 3rd emitter areas 21 to 23 are formed in the 1st, 2nd and 3rd base areas 18 to 20. The 1st base area 18 is electrically connected to the 2nd and 3rd emitter areas 22, 23. Consequently 1st and 2nd drive step transistors 12, 13 respectively composed of the 2nd and 3rd base areas 19, 20 and the 2nd and 3rd emitter areas 22, 23 and Darlington connected to a power step transistor composed of the collector area 15, the 1st base area 18 and the 1st emitter area 21 are constituted.

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