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1. 发明专利

JP2008077625A System and method for processing user defined extended operation 审中-公开
标题翻译：用于处理用户定义的扩展操作的系统和方法
公开(公告)号：JP2008077625A
公开(公告)日：2008-04-03
申请号：JP2007008660
申请日：2007-01-18
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM HEE SEOK
IPC分类号： G06F9/30
CPC分类号： G06F9/3877 , G06F9/3017 , G06F9/3885
摘要： PROBLEM TO BE SOLVED: To provide a system and method capable of processing a primitive operation and a user defined extended operation so as to enhance the efficiency of arithmetic processing using a software pipeline.
SOLUTION: An arithmetic processing system for processing an operation of a computer program includes a plurality of functional units FU which are operable to process the primitive operation, and a processor which is operable to process the extended operation according to a control of each of the functional units.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够处理原始操作和用户定义的扩展操作的系统和方法，以便提高使用软件流水线的算术处理的效率。解决方案：用于处理计算机程序的操作的算术处理系统包括可操作以处理原语操作的多个功能单元FU和可操作以根据每个的控制来处理扩展操作的处理器的功能单位。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008077627A Method and system for early z test in three-dimensional image rendering 有权
标题翻译：用于三维图像渲染的早期Z测试的方法和系统
公开(公告)号：JP2008077627A
公开(公告)日：2008-04-03
申请号：JP2007093766
申请日：2007-03-30
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： MIN KYOUNG JUNE , KIM JONG MYON , KIM HEE SEOK , KIM JEONG WOOK , KIM SUK JIN
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： PROBLEM TO BE SOLVED: To provide a method and system for an early Z test which eliminates performing of rasterization in a tile unit with respect to a three-dimensional model not displayed from a user, and consequently simplifies an arithmetic operation required for rendering, in a tile-based three-dimensional rendering. SOLUTION: The early Z test method includes: segmenting a scene into a plurality of tiles; selecting one from among a plurality of triangles constituting a three-dimensional model of a rendering object and selecting a first tile which has a tile Z value less than a minimum Z value of the selected triangle from among the plurality of tiles; and performing rendering with respect to a selected triangle in remaining triangles excluding the first tile. The minimum Z value of each triangle is preferably equal to the minimum value among Z values of three vertexes of the triangle. The tile Z value of each tile is preferably equal to the minimum value among respective maximum Z values of triangles that completely include the tile. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种早期Z测试的方法和系统，其消除了相对于不从用户显示的三维模型的平铺单元中的光栅化，并且因此简化了对于渲染，在基于瓦片的三维渲染中。解决方案：早期Z检验方法包括：将场景分割成多个瓦片; 从构成所述渲染对象的三维模型的多个三角形中选择一个，并从所述多个瓦片中选择具有小于所选择的三角形的最小Z值的瓦片Z值的第一瓦片; 并且对除了第一图块之外的剩余三角形中的所选三角形进行绘制。每个三角形的最小Z值优选等于三角形的三个顶点的Z值中的最小值。每个瓦片的瓦片Z值优选地等于完全包括瓦片的三角形的各个最大Z值中的最小值。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2011110695A Wafer polishing device 审中-公开
标题翻译：抛光抛光装置
公开(公告)号：JP2011110695A
公开(公告)日：2011-06-09
申请号：JP2010215425
申请日：2010-09-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： ROH JUNG HYUN , KIM HEE SEOK , SHIN HWA SU , HAN JUN SOO
IPC分类号： B24B41/047 , B24B7/04 , B24D7/06 , H01L21/304
CPC分类号： B24B7/228 , B24B37/10 , B24B37/30 , B24B41/047
摘要： PROBLEM TO BE SOLVED: To provide a wafer polishing device minimizing the replacing frequency of a wheel tip, by maximizing the replacing period of the wheel tip via a height adjustment of the wheel tip.
SOLUTION: This wafer polishing device includes a spindle shaft 130 rotating by a main motor, a wheel shank 140 freely rotatable by being joined in the axial direction to the spindle shaft 130, a moving shaft 160 rotating by being joined by a gear to the spindle shaft 130, and the wheel tip 110 joined to the moving shaft 160 and constituted and arranged so as to polish a wafer by being supported by the wheel shank 140.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：将要解决的问题：通过经由车轮尖端的高度调节来最大化车轮末端的更换周期，提供最小化车轮前端的更换频率的晶片抛光装置。解决方案：该晶片抛光装置包括由主电机旋转的主轴130，通过沿轴向与主轴130接合而可自由旋转的轮柄140;移动轴160，其通过齿轮连接到移动轴160并构成并布置成通过由轮柄140支撑来抛光晶片。（C）2011年，JPO和INPIT

4. 发明专利

JP2008130078A Profiler for optimizing processor architecture and application 有权
标题翻译：用于优化处理器架构和应用的配置文件
公开(公告)号：JP2008130078A
公开(公告)日：2008-06-05
申请号：JP2007169966
申请日：2007-06-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： YOO DONG-HOON , RYU SOO JUNG , KIM JEONG WOOK , KIM HONG-SEOK , KIM HEE SEOK
IPC分类号： G06F17/50 , G06F11/00
CPC分类号： G06F8/443 , G06F17/5045 , G06F2217/68
摘要： PROBLEM TO BE SOLVED: To provide a profiler, which provides information required for optimizing at least one of an application specific architecture processor and a program. SOLUTION: The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种分析器，其提供优化应用特定架构处理器和程序中的至少一个所需的信息。分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用专用架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2008204429A Method for enabling processor to speculatively execute load command and processor of adopting this method 审中-公开
标题翻译：将处理器用于特殊执行装载指令的方法和采用该方法的处理器
公开(公告)号：JP2008204429A
公开(公告)日：2008-09-04
申请号：JP2007212681
申请日：2007-08-17
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM HONG-SEOK , KIM HEE SEOK , KIM JEONG WOOK , KIM SUK JIN
IPC分类号： G06F9/38
CPC分类号： G06F9/3842
摘要： PROBLEM TO BE SOLVED: To provide a processor capable of improving performance in the processor, by eliminating a malfunction of an input-output device, breaking and deletion of input-output associated data by access to an input-output mapping memory, without adding hardware, by speculatively executing a load command like software, when executing a branch command.
SOLUTION: This processor determines whether or not its load command is a command associated to a physical memory area when receiving the load command when executing the branch command, and desirably determines whether or not an identifier of indicating the fact of being associated to the physical memory area is included in its load command. The processor executes its load command while a delay is caused when executing the branch command when determining that its load command is associated to the physical memory area.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种能够改善处理器性能的处理器，通过消除输入输出设备的故障，通过访问输入 - 输出映射存储器来断开和删除输入 - 输出相关数据，当执行分支命令时，通过推测性地执行诸如软件的加载命令来添加硬件。解决方案：当执行分支命令时，该处理器确定其负载命令是否是与物理存储器区域相关联的命令，并且期望地确定指示与物理内存区域包含在其加载命令中。当确定其加载命令与物理内存区域相关联时，执行分支命令时，处理器执行其加载命令，同时导致延迟。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008027418A Method and system for tile binning using half-plane edge function 有权
标题翻译：使用半平面边缘函数的方法和系统
公开(公告)号：JP2008027418A
公开(公告)日：2008-02-07
申请号：JP2006305390
申请日：2006-11-10
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： MIN KYOUNG JUNE , KIM JEONG WOOK , KANG DONG SOO , KIM SUK JIN , KIM HEE SEOK , JEONG SEOK-YUN , WOO SANG-OAK
IPC分类号： G06T11/00
CPC分类号： G06T15/00
摘要： PROBLEM TO BE SOLVED: To provide a method and a system for tile binning using a half-plane edge function in tile-based three-dimensional rendering. SOLUTION: In the tile binning method and system, a scene for rendering a triangle is divided into a plurality of tiles, and based on an identification value using the half-edge function at tile nodes of each of the tiles, a tile including an entirety or a part of the triangle is identified from the tiles. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在基于瓦片的三维渲染中使用半平面边缘功能的瓦片合并的方法和系统。解决方案：在瓦片合并方法和系统中，用于渲染三角形的场景被划分为多个瓦片，并且基于使用每个瓦片的瓦片节点处的半边缘功能的识别值，瓦片包括从瓦片识别三角形的整体或部分。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008204428A Memory access method using three dimensional address mapping 有权
标题翻译：使用三维地址映射的存储器访问方法
公开(公告)号：JP2008204428A
公开(公告)日：2008-09-04
申请号：JP2007201534
申请日：2007-08-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JONG MYON , RYU SOO JUNG , YOO DONG-HOON , KIM HONG-SEOK , KIM HEE SEOK , KIM JEONG WOOK , MIN KYOUNG JUNE
IPC分类号： G06F12/02
CPC分类号： G06F8/443 , G06F8/447 , G06F12/0207
摘要： PROBLEM TO BE SOLVED: To provide a method and device for efficiently accessing a memory accessed by a triple loop included in a program. SOLUTION: A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program (a is the number of values which the innermost loop variable of the triple loop may have, and b is the number of values which a middle loop variable of the triple loop may have, and c is the number of values which the outermost loop variable of the triple loop may have); obtaining a start address of the memory accessed by the triple loop; and obtaining a×b×c number of addresses of the memory accessed by the triple loop using the start address and a function. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于有效访问由程序中包括的三重回路访问的存储器的方法和装置。存储器访问方法包括：从程序中的三循环访问存储器的程序代码获得a，b和c（a是三重循环的最内循环变量的值的数量 have，b是三重循环的中间循环变量可能具有的值的数量，c是三重循环的最外循环变量可能具有的值的数量）; 获取由三重回路访问的存储器的起始地址; 并使用起始地址和功能获得由三重回路访问的存储器的×b×c个地址。版权所有（C）2008，JPO＆INPIT

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