专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2005051218A Output driver for reducing coupling noise and method for reducing coupling noise 审中-公开
标题翻译：用于减少耦合噪声的输出驱动器和减少耦合噪声的方法
公开(公告)号：JP2005051218A
公开(公告)日：2005-02-24
申请号：JP2004198063
申请日：2004-07-05
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： CHUNG IN-YOUNG
IPC分类号： H01L27/04 , G11C7/10 , H01L21/822 , H03K17/16 , H03K17/687 , H03K19/003
CPC分类号： H03K19/00361
摘要： PROBLEM TO BE SOLVED: To provide an output driver and method for reducing the coupling noise.
SOLUTION: The output driver for reducing the coupling noise comprises a first transistor, a second transistor, and a noise filter part. In the output driver, the first transistor has a first end connected to a first voltage, a second end connected to a first node, and data applied to the gate. The second transistor has a first end connected to the first node and a second end connected to the output node. The noise filter can be constituted of a capacitor connected between the gate of the first transistor and the gate of the second transistor. A coupling capacitor between the gate of the second transistor and the output node and a coupling capacitor between the gate of the second transistor and the first node can remove the coupling noise, which occurs on the gate of the second transistor, by using the data applied to the gate of the first transistor.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于减少耦合噪声的输出驱动器和方法。解决方案：用于降低耦合噪声的输出驱动器包括第一晶体管，第二晶体管和噪声滤波器部分。在输出驱动器中，第一晶体管具有连接到第一电压的第一端，连接到第一节点的第二端和施加到门的数据。第二晶体管具有连接到第一节点的第一端和连接到输出节点的第二端。噪声滤波器可以由连接在第一晶体管的栅极和第二晶体管的栅极之间的电容器构成。在第二晶体管的栅极和输出节点之间的耦合电容器和第二晶体管的栅极与第一节点之间的耦合电容器可以通过使用所应用的数据来消除在第二晶体管的栅极上发生的耦合噪声到第一晶体管的栅极。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2003188927A DATA RECEIVER, AND DATA RECEPTION METHOD 审中-公开
公开(公告)号：JP2003188927A
公开(公告)日：2003-07-04
申请号：JP2002308273
申请日：2002-10-23
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG IN-YOUNG
IPC分类号： H04L25/02 , H03K3/356 , H03K5/02 , H03K5/08 , H03K5/24 , H04L1/00 , H04L25/45
摘要： PROBLEM TO BE SOLVED: To provide a data receiver using a signal integration system so as to reduce high frequency noise generated in the case of detecting data at high speed, and a data reception method. SOLUTION: This data receiver is equipped with an integrating and amplifying circuit and a sensing and amplifier circuit, and the integrating and amplifying circuit integrates and amplifies the difference between a pair of differential reference signals and input data, and outputs the first differential signals in a pair and the second differential signals in a pair, and the sensing and amplifier circuit senses and amplifies the difference between the first differential signals in a pair and the difference between the second differential signals in a pair thereby detecting the above input data. According to the data receiver and the data reception method using the signal integration system, high frequency noise generated in the case of detecting data at high speed can be reduced, and also according to a data receiver and a data reception method which detect data by integrating and amplifying signals being inputted through two reference signal lines and a data line, the data can be detected at high speed and accurately by a differential signal system insensitively to the change of pressure, voltage, and temperature. COPYRIGHT: (C)2003,JPO

3. 发明专利

JP2004007635A CODE CONVERTER, DIGITAL / ANALOG CONVERTER, AND DELAY LOCKED LOOP CIRCUIT 审中-公开
公开(公告)号：JP2004007635A
公开(公告)日：2004-01-08
申请号：JP2003125888
申请日：2003-04-30
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG IN-YOUNG
IPC分类号： H03M1/68 , G11C7/16 , G11C7/22 , H03L7/081 , H03L7/089 , H03M1/06 , H03M1/08 , H03M1/66 , H03M1/74 , H03M7/00
摘要： PROBLEM TO BE SOLVED: To provide a digital / analog converter the surface area on an integrated circuit of which can be reduced capable of decreasing noise caused in its output. SOLUTION: The digital / analog converter comprises an escalator code generator and an escalator code / analog converter. The generator expresses a number whose lowest digit expresses 10 with a hybrid code having a coin code part and a cache code part in order to eliminate a multi-bit change in the cache code part following to a change in a count direction and expresses its count in a first direction by a sum of the coin code and the cache code. The generator changes the coin code when the cache code stays the same state until the count capability of the coin code is exceeded and the count changes its direction and the generator can change the cache code in this case. The circulation between numbers adjacent to each other whose lowest digit expressed 10 is absorbed by the coin code part while the cache code is kept in the same state. COPYRIGHT: (C)2004,JPO

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式