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1. 发明专利

JP2004164482A Random number generation device 有权
公开(公告)号：JP2004164482A
公开(公告)日：2004-06-10
申请号：JP2002331884
申请日：2002-11-15
申请人： Mathematical Design Research Institute , Sanyo Electric Co Ltd , Sanyo Semicon Device Co Ltd , 三洋セミコンデバイス株式会社 , 三洋電機株式会社 , 株式会社数理設計研究所
发明人： MEYA MASATO , TAMAOKI HARUAKI , IKETANI AKIRA
IPC分类号： G06F7/58 , G09C1/00 , H03K3/84
CPC分类号： G06F7/588 , G06F7/584
摘要： PROBLEM TO BE SOLVED: To generate a random number which is difficult to predict with more higher safety in application of such as an encryption algorithm. SOLUTION: The random number generation device 10 is provided with a plurality of pseudo random number generation parts 12a and 12b each capable of outputting random numbers of a predetermined pseudo random number series, an output random number generation part 14 generating an output random number on the basis of outputs of the plurality of pseudo random number generation parts 12a and 12b, a physical random number generator 16 generating physical random numbers, and a change over part 18 changing whether or not to update an output value of the pseudo random number generation part 12b on the basis of the physical random number generated by the physical random number generator 16. By such a configuration, which pseudo random number series is the output random number based upon is randomly changed on the basis of the physical random number, and prediction becomes much harder in comparison with a conventional random number. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2004013523A Random number generating circuit 有权
公开(公告)号：JP2004013523A
公开(公告)日：2004-01-15
申请号：JP2002166047
申请日：2002-06-06
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： MEYA MASATO
IPC分类号： G06F7/58
摘要： PROBLEM TO BE SOLVED: To provide a random number generating circuit capable of generating a physical random number effectively by a simple circuit for solving a problem such as a predictable generation pattern of a pseudo random number having periodicity. SOLUTION: Serial connection of a resistor Rs and an NPN transistor Q1 is arranged between a power source VCC and a gland. A base of a transistor Q2 having an emitter connected to the gland is connected to a short-circuited collector base in the transistor Q1. A collector of the transistor Q2 is connected to the power source VCC via a resistor RL, and the collector serves as an output end. The transistors Q1 and Q2 constitute a current mirror and let the same current flow. A base voltage of the transistor Q1 is VBE, by which current flowing through the resistor Rs is decided, and a direct current component of an output is decided. Then, thermal noise of the resistor Rs is amplified to be outputted. COPYRIGHT: (C)2004,JPO

3. 发明专利

JPH0784588A DELAY CIRCUIT 失效
公开(公告)号：JPH0784588A
公开(公告)日：1995-03-31
申请号：JP18909593
申请日：1993-06-30
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： H03K5/13 , G10K15/12 , H03H17/00 , H03H17/08
摘要： PURPOSE:To efficiently initialize a memory by routing an input signal. CONSTITUTION:The digital data outputted from an A/D converter 10 are stored in the memory 12, and the data read out from the memory 12 are converted to an analog signal by a D/A converter 14. Then, by making the read data from the memory 12 the data written before a prescribed time, a prescribed delay signal is obtained. Then, when a delay time is revised by switching a mode, the input signal is muted by a switch 50, and the signal in a soundless state is written in the memory 12, and the memory 12 is initialized. Thus, the memory 12 is initialized surely with simple constitution.

4. 发明专利

JPH04183100A BALANCE ADJUSTING CIRCUIT 失效
公开(公告)号：JPH04183100A
公开(公告)日：1992-06-30
申请号：JP31191790
申请日：1990-11-16
申请人： SANYO ELECTRIC CO
发明人： YAMADA SUSUMU , MEYA MASATO
IPC分类号： H04S7/00
摘要： PURPOSE:To cancel balance adjustment immediately after a non-adjustment period continues for more than a prescribed period by forming a count circuit as an up/down type and discriminating a count direction and an initial value with the initial value as the intermediate value of a count range. CONSTITUTION:An up/down type count circuit 19 is provided to execute counting and to set the initial value at the intermediate value of the count range with the output signal of an oscillation circuit 16 as a clock. Since it can be discriminated whether the count direction is up or down to the initial value only by observing whether the most-significant bit of the count value of this count circuit 19 is '0' or '1', the count value of the count circuit 19 is gradually changed toward the initial value. When it is detected that the count value returns to the initial value, the count operation of the count circuit 19 is stopped. Thus, when the non-adjustment period continues for more than the prescribed value, the balance adjustment can be immediately canceled.

5. 发明专利

JPH04160899A BALANCE ADJUSTMENT DEVICE 失效
公开(公告)号：JPH04160899A
公开(公告)日：1992-06-04
申请号：JP28748290
申请日：1990-10-24
申请人： SANYO ELECTRIC CO
发明人： ISHIKAWA TSUTOMU , MEYA MASATO
IPC分类号： H04S7/00
摘要： PURPOSE:To reduce the adjustment time by applying a test signal to an output side of the balance adjustment circuit so as to eliminate the need for re-adjustment of the balance adjustment circuit even when the test mode is set. CONSTITUTION:The adjustment device is provided with a test signal generator 5 not requiring balance adjustment between channels and 1st and 2nd switches 11, 12 selecting either an output signal of a balance adjustment circuit 6 or an output signal of the test signal generator 5 and outputting the selected output. Then an output of the test signal generator 5 generating a test signal in which levels of left/right stereo signal are equal to each other is generated to an output of the balance adjustment circuit 6 by using the 1st and 2nd switches 11, 12. Thus, even when the mode is set tentatively to the test mode, since the balance adjustment circuit keeps a preceding adjustment value, no re-adjustment is required and the adjustment time is reduced.

6. 发明专利

JPH0457500A BALANCE ADJUSTING CIRCUIT 失效
公开(公告)号：JPH0457500A
公开(公告)日：1992-02-25
申请号：JP16880990
申请日：1990-06-27
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO , ISHIKAWA TSUTOMU
IPC分类号： H04S7/00 , H03G3/20 , H03G3/30
摘要： PURPOSE:To correct by adjust balance among channels by counting directions according to direction signals after defining the output signal of an oscillation circuit as a clock, and attenuating signals passing through each channel according to the output signal of a decoder which decodes the counted value. CONSTITUTION:An oscillation circuit 21 operates according to a timing signal obtained from a discrimination circuit 20. For example, when right and left stereoscopic signals at almost the same levels are impressed to right and left input terminals 14 and 13, the value of the output signal of a signal generating circuit 19 is close to a reference voltage Vref. Because of this, the output signal of the discrimination circuit 20 goes to an L level, and the oscillation circuit 21 starts the operation. Then, the oscillation circuit 21 continues the oscillation as long as an output signal Vx of the signal generating circuit 19 is within the ranges of reference voltages VA and VB of the discrimination circuit 20. Therefore, a decoder 25 decodes successively the counted value of a counting circuit 24, and controls right and left attenuating circuits 18 and 17 so as to hold a balance state.

7. 发明专利

JP2009272958A Delay circuit 审中-公开
标题翻译：延时电路
公开(公告)号：JP2009272958A
公开(公告)日：2009-11-19
申请号：JP2008122607
申请日：2008-05-08
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： MEYA MASATO , YASUMIBA TAKASHI , SERIZAWA SHUNSUKE
IPC分类号： H04N9/78 , H03H7/30
摘要： PROBLEM TO BE SOLVED: To appropriately suppress circuit scale of a delay circuit used for a video signal processing circuit. SOLUTION: In the delay circuit configured as a sample/hold circuit based on switched capacitor technologies, in a case where the number of memory units 111 is to be reduced, a voltage fixing circuit 140 is included which is provided between a signal line L10 connected to a non-inverted input terminal of a differential amplifier 150 and a reference power source, includes a third switching element T1 for fixing the signal line 10 to a voltage Vr of a reference power source when turned on, turns off the third switching element T1 with an output A1 of a flip-flop FF1 on a first stage of a shift register 120, and turns on the third switching element T1 with an output of a flip-flop FF5 on a final stage of the shift register 120. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：适当地抑制用于视频信号处理电路的延迟电路的电路规模。解决方案：在配置为基于开关电容器技术的采样/保持电路的延迟电路中，在存储单元111的数量将被减少的情况下，包括电压定影电路140，其被提供在信号线路L10连接到差分放大器150的非反相输入端子和参考电源，包括用于在接通时将信号线10固定为参考电源的电压Vr的第三开关元件T1将第三在移位寄存器120的第一级具有触发器FF1的输出A1的开关元件T1，并且在移位寄存器120的最后级的触发器FF5的输出端接通第三开关元件T1。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009060427A Video signal processing circuit 审中-公开
标题翻译：视频信号处理电路
公开(公告)号：JP2009060427A
公开(公告)日：2009-03-19
申请号：JP2007226574
申请日：2007-08-31
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： MEYA MASATO , ISHII SATOYUKI , SERIZAWA SHUNSUKE
IPC分类号： H04N9/78
摘要： PROBLEM TO BE SOLVED: To appropriately extract luminance signals and chroma signals from video signals without the need of an A/D converter.
SOLUTION: The video signal processing circuit includes: a first switched capacitor filter wherein a horizontal high-pass filter function using first video signals for one horizontal scanning period and second video signals for which the former signals are delayed and a vertical low pass filter function are combined; a second switched capacitor wherein the horizontal high-pass filter function using the second video signals and third video signals for which the former signals are delayed and the vertical low pass filter function are combined; first and second comparators for outputting a first correlation degree between the first and second video signals and a second correlation degree between the second and third video signals by the size comparison of each output of the first and second switched capacitor filters; and a Y/C separation circuit for separating the video signals into the luminance signals and the chroma signals using the first and second video signals or the second and third video signals on the basis of the first and second correlation degrees.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：适当地从视频信号中提取亮度信号和色度信号，而不需要A / D转换器。视频信号处理电路包括：第一开关电容滤波器，其中使用用于一个水平扫描周期的第一视频信号的水平高通滤波器功能和前一个信号被延迟的第二视频信号和垂直低通滤波器过滤功能组合; 第二开关电容器，其中使用第二视频信号的水平高通滤波器功能和前一个信号被延迟的第三视频信号和垂直低通滤波器功能被组合; 第一和第二比较器，用于通过第一和第二开关电容滤波器的每个输出的尺寸比较来输出第一和第二视频信号之间的第一相关度和第二和第三视频信号之间的第二相关度; 以及Y / C分离电路，用于基于第一和第二相关度，使用第一和第二视频信号或第二和第三视频信号将视频信号分离成亮度信号和色度信号。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2008085651A Analog memory 审中-公开
标题翻译：模拟记忆
公开(公告)号：JP2008085651A
公开(公告)日：2008-04-10
申请号：JP2006263209
申请日：2006-09-27
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： MEYA MASATO , SERIZAWA SHUNSUKE
IPC分类号： H04N9/78 , H03H19/00
CPC分类号： G11C27/04 , G11C27/026
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein the parasitic capacity of wiring Lout for discharge becomes large in proportion to the number of sets of switched capacitor sections SC in an analog memory using a conventional technique.
SOLUTION: The wiring Lout for discharge is divided into a plurality of portions to reduce a total amount of parasitic capacity, and the number of second MOS transistors Out connected to the non-inverted output terminal + of the operational amplifier OP is reduced simultaneously. Before and after a wiring selection switch SL is changed, both the pieces of wiring Lout for discharge related to current and next stages are connected to the non-inverted output terminal + of the operational amplifier OP to prevent any difference in the influence of the parasitic capacity.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题为了解决使用常规技术的模拟存储器中的用于放电的布线Lout的寄生电容与开关电容器部分SC的组数成比例变大的问题。解决方案：用于放电的布线Lout被分成多个部分以减少寄生电容的总量，并且连接到运算放大器OP的非反相输出端+的第二MOS晶体管Out的数量减少同时。在布线选择开关SL改变之前和之后，与电流和下一级相关的用于放电的两个布线Lout连接到运算放大器OP的非反相输出端+，以防止寄生的影响的任何差异容量。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2004013520A Thermal noise generation circuit 有权
公开(公告)号：JP2004013520A
公开(公告)日：2004-01-15
申请号：JP2002166028
申请日：2002-06-06
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： MEYA MASATO , KANEKO SATOSHI
IPC分类号： G06F7/58
摘要： PROBLEM TO BE SOLVED: To provide a thermal noise generation circuit outputting thermal noise effectively by a simple circuit and to improve temperature characteristics of a direct current component especially. SOLUTION: A serial connection of resistors R1 and R2 is arranged between a power source VCC and a gland. The resistors R1 and R2 are constructed of polysilicon and provided with negative temperature characteristics. The dimension of the thermal noise is proportional to 4kT (k: a Boltzmann constant, T: an absolute temperature) and R (a resistance value). When the resistor has the negative temperature characteristic, the fluctuation of the generated thermal noise according to a temperature can be reduced. COPYRIGHT: (C)2004,JPO

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