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1. 发明专利

JP2005190195A Microcontroller 有权
标题翻译：微控制器
公开(公告)号：JP2005190195A
公开(公告)日：2005-07-14
申请号：JP2003431114
申请日：2003-12-25
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SAKURAI KOHEI , MORITA YUICHIRO , KANEKAWA NOBUYASU , HOSHINO MASATOSHI , SHIMAMURA KOTARO , YAMADA HIROMICHI , TANAKA SATOSHI , YADA NAOKI
IPC分类号： G06F15/78 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To reduce a load of peripheral module control on a CPU even if A/D conversion is required to be executed in various patterns, such as short period sampling and over-sampling of analog signals, with increasing control precision in a control system. SOLUTION: In a microcontroller 1, a timer unit 4 can generate and output a plurality of types of A/D conversion request signals ADREQt0 to ADREQtk corresponding to a plurality of A/D conversion processing patterns of different A/D conversion processing attributes to an A/D converter 5 to start and execute A/D conversion. The attributes of the A/D conversion request signals ADREQt that are trigger signals to A/D conversion, such as an output period, an output count, a mode, counter selection and enabling, can be set in a control register built in the timer unit 4. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使需要以各种模式执行A / D转换，例如模拟信号的短周期采样和过采样，减少CPU上的外围模块控制的负载，随着控制的增加控制系统的精度。解决方案：在微控制器1中，定时器单元4可以生成并输出对应于不同A / D转换处理的多个A / D转换处理模式的多种类型的A / D转换请求信号ADREQt0至ADREQtk 属性到A / D转换器5以启动和执行A / D转换。可以在内置在定时器中的控制寄存器中设置作为A / D转换的触发信号的A / D转换请求信号ADREQt的属性，例如输出周期，输出计数，模式，计数器选择和使能单位4.版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2010170579A Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：JP2010170579A
公开(公告)日：2010-08-05
申请号：JP2010095773
申请日：2010-04-19
申请人： Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人： MATSUO TOSHIHIRO , ISHIKURA HIROMICHI , MUKAI HIROFUMI , YADA NAOKI
IPC分类号： G06F15/78
摘要： PROBLEM TO BE SOLVED: To improve write reliability when a write processing program is held in an on-chip non-volatile memory. SOLUTION: The data processor has: a CPU; a volatile memory (RAM); an electrically writable nonvolatile memory which has a first storage area for storing a write program and a transfer control program for transferring the program to the volatile memory and a second storage area which causes the CPU to execute the program to write information and stores the control program processed by the CPU in a first operation mode; and a storage circuit (FCCS) where the CPU sets control information (SCO) in the first operation mode. The CPU executes the transfer control program in response to the setting of control information to the storage circuit and transfers the write program to the volatile memory, and the CPU is returned to the first operation mode for executing the control program in response to completion of transfer of the write program to the volatile memory. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了在写入处理程序保存在片上非易失性存储器中时提高写入可靠性。
解决方案：数据处理器具有：CPU; 易失性存储器（RAM）; 具有用于存储写入程序的第一存储区域和用于将程序传送到易失性存储器的传送控制程序的电可写非易失性存储器和使CPU执行程序以写入信息并存储控制程序的第二存储区域由CPU在第一操作模式下处理; 以及其中CPU在第一操作模式中设置控制信息（SCO）的存储电路（FCCS）。 CPU响应于向存储电路的控制信息的设置执行传送控制程序，并将写入程序传送到易失性存储器，并且CPU响应于传送完成而返回到用于执行控制程序的第一操作模式的写入程序到易失性存储器。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2008186476A Microcomputer 审中-公开
标题翻译：微机
公开(公告)号：JP2008186476A
公开(公告)日：2008-08-14
申请号：JP2008059286
申请日：2008-03-10
申请人： Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人： YADA NAOKI , ISHIKAWA EIICHI
IPC分类号： G06F12/02 , G06F12/00 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer in which onboard writing can be performed by user exclusive use communication protocol even if serial interface is not made on a mounting board, and in which the user exclusive use communication protocol codes are not destroyed even if the microcomputer runs away. SOLUTION: The microcomputer is provided with a CPU (2), a non-volatile memory (13), and a RAM (3). The non-volatile memory includes a first domain (Tmat) which possesses a communication control program processed by the CPU, a second domain (Umat) in which interface with the outside is established by the processing of the communication control program by the CPU and deleting and writing are enabled, and a third domain (Mmat) in which interface with the outside is established by the processing of the communication control program by the CPU, deleting and writing are enabled, and deleting and writing are enabled by the processing of the program of the second domain by the CPU. The second domain and the third domain can be selected exclusively by a register. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种微型计算机，其中即使不在安装板上进行串行接口，并且用户专用通信协议代码不被破坏，其中可以通过用户专用通信协议执行机载写入即使微型计算机跑掉。
解决方案：微型计算机设置有CPU（2），非易失性存储器（13）和RAM（3）。非易失性存储器包括具有由CPU处理的通信控制程序的第一域（Tmat），通过CPU对通信控制程序的处理建立与外部的接口的第二域（Umat），并且删除并且启用写入，并且通过CPU对通信控制程序的处理建立了与外部接口的第三域（Mmat），删除和写入，并且通过程序的处理能够实现删除和写入的第二个域由CPU。第二个域和第三个域可以由一个寄存器专门地选择。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008022387A A/d converter and data processor 审中-公开
标题翻译： A / D转换器和数据处理器
公开(公告)号：JP2008022387A
公开(公告)日：2008-01-31
申请号：JP2006193503
申请日：2006-07-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TSUNAKAWA HIROYUKI , YADA NAOKI
IPC分类号： H03M1/12 , G06F3/05
摘要： PROBLEM TO BE SOLVED: To improve performance of a data processor provided with an A/D converter.
SOLUTION: The A/D converter includes a data register (221), an A/D conversion value addition mode selecting register (202), and an A/D conversion control circuit (222) for controlling the A/D converter (208) to continuously execute for a plurality of times the A/D conversion of the same analog signal when the A/D conversion value addition mode is set to the A/D conversion value addition mode selecting register and storing a sum of such conversion values to the data register. In the data processor including such A/D converter, improvement in the performance is possible, because it is not required to execute the summing average processing of the A/D conversion result after an output data of data register in the A/D converter is extracted.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高A / D转换器提供的数据处理器的性能。解决方案：A / D转换器包括数据寄存器（221），A / D转换值相加模式选择寄存器（202）和用于控制A / D转换器的A / D转换控制电路（222）（208），当将A / D转换值相加模式设置为A / D转换值相加模式选择寄存器时，连续执行相同模拟信号的A / D转换多次，并存储这种转换值到数据寄存器。在包括这种A / D转换器的数据处理器中，由于在A / D转换器中的数据寄存器的输出数据是在A / D转换器的输出数据之后不需要执行A / D转换结果的求和平均处理提取。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007104708A Data processing method 审中-公开
标题翻译：数据处理方法
公开(公告)号：JP2007104708A
公开(公告)日：2007-04-19
申请号：JP2006318039
申请日：2006-11-27
申请人： Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人： YADA NAOKI , ISHIKAWA EIICHI
IPC分类号： H03M13/01 , G06F11/10 , G06F12/16 , H04L1/00
摘要： PROBLEM TO BE SOLVED: To provide a technology for efficient ECC processing by means of a software. SOLUTION: When an ECC code with respect to n-bit data is set as m-bit, a matrix table containing mutually different m-bit binary numbers arrayed in m+n columns is formed as a fixed data in a flash memory storage area (20Bb), and an ECC code generation program process is made to refer to it. In the ECC code generation, a matrix table column value, corresponding to bit position of a data logical value "1", is XORed per bit in the row direction, and the resulting m-bit value is defined as the ECC code, which is then appended to the data to generate an m+n bit code word. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过软件进行高效ECC处理的技术。解决方案：当将相对于n位数据的ECC代码设置为m位时，将包含以m + n列排列的相互不同的m位二进制数的矩阵表形成为闪存中的固定数据存储区域（20Bb）和ECC代码生成程序处理。在ECC代码生成中，对应于数据逻辑值“1”的位位置的矩阵表列值在行方向上每位被异或，并且将所得到的m位值定义为ECC代码，其是然后附加到数据以生成m + n位码字。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006288197A Semiconductor integrated circuit and microcomputer 有权
标题翻译：半导体集成电路和微型计算机
公开(公告)号：JP2006288197A
公开(公告)日：2006-10-19
申请号：JP2006118632
申请日：2006-04-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISHIKAWA EIICHI , SAITO YASUYUKI , SATO NARIHISA , YADA NAOKI , MATSUBARA KIYOSHI
IPC分类号： H02M3/07 , G05F1/56 , G11C16/06 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To improve efficiency of voltage step-up, in a flash memory built-in in a microcomputer. SOLUTION: The semiconductor integrated circuit is provided with a booster circuit for generating step-up voltage by receiving prescribed voltage. The booster circuit, for generating the step-up voltage, comprises a charge pump circuit (47) having a step-up node connected to a MOS transistor and a capacitor, and a switching means (460) for switching substrate bias voltage so that the threshold of the MOS transistor, decreases from starting of step-up operation, until voltage output by the booster circuit reaches the step-up voltage. The threshold voltage of the MOS transistor becomes small, thereby electric charges are easily moved via the MOS transistor operating the charge pump. This fact improves the step-up operating efficiency so as to shorten the time until the prescribed step-up voltage is obtained. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在微型计算机内置的闪速存储器中提高升压电压的效率。解决方案：半导体集成电路设置有用于通过接收规定电压来产生升压电压的升压电路。用于产生升压电压的升压电路包括具有连接到MOS晶体管和电容器的升压节点的电荷泵电路（47），以及用于切换衬底偏置电压的开关装置（460），使得 MOS晶体管的阈值从升压操作开始降低，直到由升压电路输出的电压达到升压电压。 MOS晶体管的阈值电压变小，电容容易通过操作电荷泵的MOS晶体管移动。该事实提高了升压操作效率，从而缩短了达到规定的升压电压之前的时间。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006140241A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2006140241A
公开(公告)日：2006-06-01
申请号：JP2004327192
申请日：2004-11-11
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MOMII MASATO , YADA NAOKI , IWABUCHI MASARU
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822
CPC分类号： G11C7/1045 , G11C7/222
摘要： PROBLEM TO BE SOLVED: To reduce the size of a semiconductor integrated circuit device by considerably reducing the circuit area of a control information holding means which holds control information used for the trimming etc., of an analog circuit etc.
SOLUTION: A fuse module 4 which holds the trimming information of an internal oscillating circuit module is composed of information writing fuse circuits 20
1 -20
n in which the trimming information is written by fusing/non-fusing an information writing fuse 25, a reference fuse circuit 20 which discriminates whether the fuse 25 is fused or not, and a current/voltage converter 21. Since the reference fuse circuit 20 and current/voltage converting section 21 are commonly used for the information writing fuse circuits 20
1 -20
n , the circuit area of the fuse module 4 can be reduced significantly.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过显着地减少用于模拟电路等的修整等的控制信息的控制信息保持装置的电路面积，来减小半导体集成电路器件的尺寸。解决方案：保存内部振荡电路模块的修整信息的保险丝模块4由写入修剪信息的信息写入熔丝电路20 -20 n 组成通过融合/不熔化信息写入保险丝25，鉴别熔丝25是否熔断的参考熔丝电路20以及电流/电压转换器21.由于参考熔丝电路20和电流/电压转换部21是通常用于信息写入熔丝电路20 -20 n ，可以显着降低熔丝模块4的电路面积。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005191810A Digital/analog converter and microcomputer 审中-公开
标题翻译：数字/模拟转换器和微型计算机
公开(公告)号：JP2005191810A
公开(公告)日：2005-07-14
申请号：JP2003429291
申请日：2003-12-25
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KANEKAWA NOBUYASU , HOSHINO MASATOSHI , SAKURAI KOHEI , YAMADA HIROMICHI , SHIMAMURA KOTARO , MORITA YUICHIRO , TANAKA SATOSHI , YADA NAOKI
IPC分类号： H03M1/12 , H03M3/02
摘要： PROBLEM TO BE SOLVED: To provide an A/D converter capable of A/D conversion processing while necessary resolutions are flexibly set by analog inputs, and a microcomputer.
SOLUTION: Disclosed is the A/D converter which has an A/D control register 60 where control information on A/D conversion is set and has a function of performing oversampling while selecting one of a plurality of analog input channels AN0 to ANn. The A/D converter has a plurality of entries of conversion control information of the A/D control register 60 and also has a field where an oversampling ratio is set in each entry. According to settings of entries, an A/D conversion part 30 performs A/D conversion at a specified oversampling ratio, and a filter arithmetic circuit 10 performs filter processing with a specified filter coefficient and outputs an A/D conversion result data. Thus, the A/D conversion processing is carried out at oversampling ratios by analog inputs.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够进行A / D转换处理的A / D转换器，同时通过模拟输入灵活设置必要的分辨率和微型计算机。解决方案：公开了具有A / D控制寄存器60的A / D转换器，其中设置有关A / D转换的控制信息，并且具有执行过采样的功能，同时选择多个模拟输入通道AN0至安。 A / D转换器具有多个A / D控制寄存器60的转换控制信息条目，并且还具有在每个条目中设置过采样比的字段。根据条目的设定，A / D转换部30以规定的过采样比进行A / D转换，滤波运算电路10进行具有规定的滤波系数的滤波处理，并输出A / D转换结果数据。因此，通过模拟输入以过采样比进行A / D转换处理。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005057374A Analog/digital converter and micro controller 审中-公开
标题翻译：模拟/数字转换器和微控制器
公开(公告)号：JP2005057374A
公开(公告)日：2005-03-03
申请号：JP2003206631
申请日：2003-08-08
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MORITA YUICHIRO , SAKURAI KOHEI , KANEKAWA NOBUYASU , HOSHINO MASATOSHI , YAMADA HIROMICHI , SHIMAMURA KOTARO , TANAKA SATOSHI , YADA NAOKI
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1225
摘要： PROBLEM TO BE SOLVED: To provide an analog/digital converter having only a basic function for executing analog/digital conversion without imposing a load on a CPU by increasing the number of selection patterns of analog input channels in each analog/digital conversion with a storage capacity nearly equal to that of a prior art, and to provide a micro controller.
SOLUTION: The analog/digital converter or a DMA transfer apparatus is provided with an analog/digital conversion table having one entry or more each comprising an enable bit used to set to apply analog/digital conversion to each analog input channel and a plurality of times of bits to set the number of times of analog/digital conversion. Thus, selection patterns for analog input channels being approximately a multiple of n of those of a conventional analog/digital conversion table can be set irrespective of the storage capacity nearly equal to that of the prior art. Further, the DMA transfer apparatus is provided with the analog/digital conversion table, and even when the analog/digital converter having only the basic function is in use, optional analog/digital conversion can be executed without imposing a load on the CPU.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种仅具有执行模/数转换的基本功能的模拟/数字转换器，而不会通过增加每个模/数转换中的模拟输入通道的选择模式数来对CPU施加负载具有几乎等于现有技术的存储容量，并提供微控制器。模拟/数字转换器或DMA传送装置具有模拟/数字转换表，该模拟/数字转换表具有一个或更多个条目，每个条目包括用于设置为对每个模拟输入通道进行模拟/数字转换的使能位，以及多次位设置模拟/数字转换的次数。因此，与现有技术几乎相同的存储容量，可以设定模拟输入通道的选择模式大约是常规模拟/数字转换表的n的倍数。此外，DMA传送装置设置有模拟/数字转换表，并且即使当仅使用具有基本功能的模拟/数字转换器时，可以执行可选的模拟/数字转换，而不对CPU施加负载。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2009032908A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2009032908A
公开(公告)日：2009-02-12
申请号：JP2007195521
申请日：2007-07-27
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SASAKI TOSHIO , YASU YOSHIHIKO , MIURA YUJI , YADA NAOKI
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To reduce power consumption in a temporary operation stop state.
SOLUTION: An input/output circuit unit sends and receives input/output signals having a first voltage to and from an external terminal. An internal circuit unit operates with a second voltage different from the first voltage and has a first switch on a second-voltage or circuit-ground-potential side. The input circuit of the input/output circuit unit has an input portion which operates with the first voltage and a first level converting circuit which operates with the second voltage. the output circuit of the input/output circuit unit has a second level converting circuit which operates with the first voltage and second voltage, and an output portion and a latch which operate with the first voltage. The input/output circuit unit has a second switch on a second-voltage side or the ground-potential side of the circuit portion operating with the second voltage, and a power switch control circuit turns on the first and second switches when the internal circuit is in operation and turns off the first and second switches when in a temporary operation stop state.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了减少临时停止运行状态下的功耗。
解决方案：输入/输出电路单元向外部端子发送和接收具有第一电压的输入/输出信号。内部电路单元以不同于第一电压的第二电压工作，并且在第二电压或电路地电势侧具有第一开关。输入/输出电路单元的输入电路具有与第一电压一起工作的输入部分和与第二电压一起工作的第一电平转换电路。输入/输出电路单元的输出电路具有以第一电压和第二电压工作的第二电平转换电路，以及与第一电压一起工作的输出部分和锁存器。输入/输出电路单元具有在第二电压的第二电压侧或电路部分的接地电位侧上的第二开关，并且当内部电路为内部电路时，电源开关控制电路接通第一和第二开关并且在暂时停止状态时关闭第一和第二开关。版权所有（C）2009，JPO＆INPIT

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