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1. 发明专利

JP2008186476A Microcomputer 审中-公开
标题翻译：微机
公开(公告)号：JP2008186476A
公开(公告)日：2008-08-14
申请号：JP2008059286
申请日：2008-03-10
申请人： Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人： YADA NAOKI , ISHIKAWA EIICHI
IPC分类号： G06F12/02 , G06F12/00 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer in which onboard writing can be performed by user exclusive use communication protocol even if serial interface is not made on a mounting board, and in which the user exclusive use communication protocol codes are not destroyed even if the microcomputer runs away. SOLUTION: The microcomputer is provided with a CPU (2), a non-volatile memory (13), and a RAM (3). The non-volatile memory includes a first domain (Tmat) which possesses a communication control program processed by the CPU, a second domain (Umat) in which interface with the outside is established by the processing of the communication control program by the CPU and deleting and writing are enabled, and a third domain (Mmat) in which interface with the outside is established by the processing of the communication control program by the CPU, deleting and writing are enabled, and deleting and writing are enabled by the processing of the program of the second domain by the CPU. The second domain and the third domain can be selected exclusively by a register. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种微型计算机，其中即使不在安装板上进行串行接口，并且用户专用通信协议代码不被破坏，其中可以通过用户专用通信协议执行机载写入即使微型计算机跑掉。
解决方案：微型计算机设置有CPU（2），非易失性存储器（13）和RAM（3）。非易失性存储器包括具有由CPU处理的通信控制程序的第一域（Tmat），通过CPU对通信控制程序的处理建立与外部的接口的第二域（Umat），并且删除并且启用写入，并且通过CPU对通信控制程序的处理建立了与外部接口的第三域（Mmat），删除和写入，并且通过程序的处理能够实现删除和写入的第二个域由CPU。第二个域和第三个域可以由一个寄存器专门地选择。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007104708A Data processing method 审中-公开
标题翻译：数据处理方法
公开(公告)号：JP2007104708A
公开(公告)日：2007-04-19
申请号：JP2006318039
申请日：2006-11-27
申请人： Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人： YADA NAOKI , ISHIKAWA EIICHI
IPC分类号： H03M13/01 , G06F11/10 , G06F12/16 , H04L1/00
摘要： PROBLEM TO BE SOLVED: To provide a technology for efficient ECC processing by means of a software. SOLUTION: When an ECC code with respect to n-bit data is set as m-bit, a matrix table containing mutually different m-bit binary numbers arrayed in m+n columns is formed as a fixed data in a flash memory storage area (20Bb), and an ECC code generation program process is made to refer to it. In the ECC code generation, a matrix table column value, corresponding to bit position of a data logical value "1", is XORed per bit in the row direction, and the resulting m-bit value is defined as the ECC code, which is then appended to the data to generate an m+n bit code word. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过软件进行高效ECC处理的技术。解决方案：当将相对于n位数据的ECC代码设置为m位时，将包含以m + n列排列的相互不同的m位二进制数的矩阵表形成为闪存中的固定数据存储区域（20Bb）和ECC代码生成程序处理。在ECC代码生成中，对应于数据逻辑值“1”的位位置的矩阵表列值在行方向上每位被异或，并且将所得到的m位值定义为ECC代码，其是然后附加到数据以生成m + n位码字。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2008112568A Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：JP2008112568A
公开(公告)日：2008-05-15
申请号：JP2007326933
申请日：2007-12-19
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MATSUBARA KIYOSHI , SATO NARIHISA , ISHIKAWA EIICHI
IPC分类号： G11C29/04 , G11C16/06 , G11C29/02 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To provide a defect tolerance technique for a non-volatile memory device in which a special step is not required, without increasing access time, while suppressing increase in area. SOLUTION: A data processor includes a memory cell MC-R for redundancy and a memory cell MC-C for storing tolerance information that designates a memory cell MC to be replaced with the memory cell MC-R. When the tolerance information is written, the memory cell MC-C is selected by a tolerance bit selection circuit RSEL. The written tolerance information is initially loaded into a tolerance information latch CLAT in accordance with an instruction by a reset signal MD2. In a normal write/read operation, an address comparison circuit ACMP compares the tolerance information with address information supplied from a CPU. When the information match each other, the memory cell MC-R for redundancy is selected. When the information do not match each other, a memory cell is selected in accordance with the address information supplied from the CPU. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了在不增加访问时间的同时抑制面积增加的情况下为不需要特殊步骤的非易失性存储器件提供缺陷容差技术。解决方案：数据处理器包括用于冗余的存储单元MC-R和用于存储指定要由存储单元MC-R替换的存储单元MC的容差信息的存储单元MC-C。当公差信息被写入时，由公差位选择电路RSEL选择存储单元MC-C。写入的容差信息根据复位信号MD2的指令最初加载到公差信息锁存器CLAT中。在正常写/读操作中，地址比较电路ACMP将容差信息与从CPU提供的地址信息进行比较。当信息彼此匹配时，选择用于冗余的存储单元MC-R。当信息不匹配时，根据从CPU提供的地址信息来选择存储单元。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2006288197A Semiconductor integrated circuit and microcomputer 有权
标题翻译：半导体集成电路和微型计算机
公开(公告)号：JP2006288197A
公开(公告)日：2006-10-19
申请号：JP2006118632
申请日：2006-04-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISHIKAWA EIICHI , SAITO YASUYUKI , SATO NARIHISA , YADA NAOKI , MATSUBARA KIYOSHI
IPC分类号： H02M3/07 , G05F1/56 , G11C16/06 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To improve efficiency of voltage step-up, in a flash memory built-in in a microcomputer. SOLUTION: The semiconductor integrated circuit is provided with a booster circuit for generating step-up voltage by receiving prescribed voltage. The booster circuit, for generating the step-up voltage, comprises a charge pump circuit (47) having a step-up node connected to a MOS transistor and a capacitor, and a switching means (460) for switching substrate bias voltage so that the threshold of the MOS transistor, decreases from starting of step-up operation, until voltage output by the booster circuit reaches the step-up voltage. The threshold voltage of the MOS transistor becomes small, thereby electric charges are easily moved via the MOS transistor operating the charge pump. This fact improves the step-up operating efficiency so as to shorten the time until the prescribed step-up voltage is obtained. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在微型计算机内置的闪速存储器中提高升压电压的效率。解决方案：半导体集成电路设置有用于通过接收规定电压来产生升压电压的升压电路。用于产生升压电压的升压电路包括具有连接到MOS晶体管和电容器的升压节点的电荷泵电路（47），以及用于切换衬底偏置电压的开关装置（460），使得 MOS晶体管的阈值从升压操作开始降低，直到由升压电路输出的电压达到升压电压。 MOS晶体管的阈值电压变小，电容容易通过操作电荷泵的MOS晶体管移动。该事实提高了升压操作效率，从而缩短了达到规定的升压电压之前的时间。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2004303416A Nonvolatile storage device, microcomputer, nonvolatile semiconductor memory device, and data processor 有权
公开(公告)号：JP2004303416A
公开(公告)日：2004-10-28
申请号：JP2004183473
申请日：2004-06-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MATSUBARA KIYOSHI , SATO NARIHISA , ISHIKAWA EIICHI
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04
摘要： PROBLEM TO BE SOLVED: To provide defect relieving technology of a nonvolatile storage device in which a special process is not required, an access time is not increased, and increment of area is small. SOLUTION: A memory cell MC-R for redundancy and a memory cell MC-C for storing relieving information specifying a memory cell MC to be replaced by the memory cell MC-R are provided. Selection of the memory cell MC-C is performed by a relieving bit selecting circuit RSEL in write of relieving information. Written relieving information is loaded initially to a relieving information latch CLAT by the indication of a reset signal MD2. An address comparing circuit ACMP compares the relieving information with address information externally supplied in normal write/read. When both coincide, the memory cell MC-R for redundancy is selected. COPYRIGHT: (C)2005,JPO&NCIPI

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