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1. 发明专利

JP2010245433A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010245433A
公开(公告)日：2010-10-28
申请号：JP2009094885
申请日：2009-04-09
申请人： Panasonic Corp , パナソニック株式会社
发明人： SATO YOSHIHIRO , FUJIMOTO HIROMASA
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823842 , H01L29/495
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a p-type MIS transistor formed on a semiconductor substrate having a (110) plane as a principal surface, the performance of the p-type MIS transistor being improved more. SOLUTION: The semiconductor device includes the p-type MIS transistor PTr formed on the semiconductor substrate 10 having the (110) plane as the principal surface. The p-type MIS transistor PTr includes a first gate insulating film 13a formed on a first active region 10a of the semiconductor substrate 10, and a first gate electrode 14A composed of a first metal film 14a formed on the first gate insulating film 13a, and a first silicon film 15a formed on the first metal film 14a. The first metal film 14a has a film thickness of 1 to 10 nm. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种具有形成在具有（110）面作为主面的半导体衬底上的p型MIS晶体管的半导体器件，p型MIS晶体管的性能得到改善。解决方案：半导体器件包括形成在具有（110）面作为主面的半导体衬底10上的p型MIS晶体管PTr。 p型MIS晶体管PTr包括形成在半导体衬底10的第一有源区域10a上的第一栅极绝缘膜13a和由形成在第一栅极绝缘膜13a上的第一金属膜14a组成的第一栅电极14A和形成在第一金属膜14a上的第一硅膜15a。第一金属膜14a的膜厚为1〜10nm。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2010205768A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010205768A
公开(公告)日：2010-09-16
申请号：JP2009046449
申请日：2009-02-27
申请人： Panasonic Corp , Renesas Electronics Corp , パナソニック株式会社 , ルネサスエレクトロニクス株式会社
发明人： INOUE MASAO , SAKASHITA SHINSUKE , YASUMA MASATOSHI , YOSHIGAMI JIRO , YAMANARI SHINICHI , SATO YOSHIHIRO , YAMAMOTO KAZUHIKO , OSUGA TSUTOMU
IPC分类号： H01L29/78 , H01L21/28 , H01L21/283 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a gate structure having a side wall formed, without causing deterioration in semiconductor characteristics and reliability, in the gate structure made of a metal electrode/high-k gate insulating film. SOLUTION: The gate structure includes: a gate insulating film 2 which is provided on a semiconductor substrate 1, and which is made of a high-k dielectric material; a metal electrode 3 which is provided on the gate insulating film 2; an oxidation resistant film 4 which covers the side wall of the metal electrode 3, and which is disposed opposite the semiconductor substrate 1 with the gate insulating film 2 interposed therebetween; and a side wall 5 which is provided on the semiconductor substrate so as to cover the gate insulating film 2 and an oxidation prevention film 4. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其具有形成有侧壁的栅极结构，而不会在由金属电极/高k栅极绝缘膜制成的栅极结构中导致半导体特性和可靠性的劣化。解决方案：栅极结构包括：栅极绝缘膜2，其设置在半导体衬底1上，并且由高k电介质材料制成; 设置在栅极绝缘膜2上的金属电极3; 覆盖金属电极3的侧壁并与半导体衬底1相对设置有隔着绝缘膜2的抗氧化膜4; 以及设置在半导体基板上以覆盖栅极绝缘膜2和防氧化膜4的侧壁5.版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009088069A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009088069A
公开(公告)日：2009-04-23
申请号：JP2007253260
申请日：2007-09-28
申请人： Panasonic Corp , パナソニック株式会社
发明人： SATO YOSHIHIRO
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/768 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7847 , H01L29/7848
摘要： PROBLEM TO BE SOLVED: To form a silicon mixed crystal layer with high precision in one of the source-drain forming region of an n-type MIS transistor and the source-drain forming region of a p-type MIS transistor. SOLUTION: A first MIS transistor comprises a first sidewall 19A formed on the side face of a first gate electrode 14a and consisting of a first inside sidewall 18a having an L-shaped cross-section and a first outside sidewall 19a, a second MIS transistor comprises a second sidewall 19B formed on the side face of a second gate electrode 14b and consisting of a second inside sidewall 18b having an L-shaped cross-section and a second outside sidewall 19b, and a silicon mixed crystal layer 22 formed within a trench 21 provided in the source-drain forming region in a second active region and producing a first stress in the channel region in the second active region, and the height of the upper end of the second inside sidewall is smaller than the height of the upper end of the first inside sidewall. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在n型MIS晶体管的源极 - 漏极形成区域和p型MIS晶体管的源极 - 漏极形成区域之一中，高精度地形成硅混晶层。解决方案：第一MIS晶体管包括形成在第一栅电极14a的侧面上并由具有L形横截面的第一内侧壁18a和第一外侧壁19a形成的第一侧壁19A， MIS晶体管包括形成在第二栅电极14b的侧面上并由具有L形横截面的第二内侧壁18b和第二外侧壁19b形成的第二侧壁19B，以及形成在其内的硅混晶层22 设置在第二有源区域中的源极 - 漏极形成区域中的沟槽21，并且在第二有源区域中的沟道区域中产生第一应力，并且第二内部侧壁的上端的高度小于第二有源区域的高度第一内侧壁的上端。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008288465A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008288465A
公开(公告)日：2008-11-27
申请号：JP2007133488
申请日：2007-05-18
申请人： Panasonic Corp , パナソニック株式会社
发明人： SATO YOSHIHIRO , OGAWA HISASHI
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823857 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To accurately achieve a gate insulating film constituted of insulating materials different for a first MIS transistor and a second MIS transistor. SOLUTION: An N-type MIS transistor NTr comprises a first gate insulating film 105a formed on a first active region 100a in a semiconductor substrate 100 and a first gate electrode 108a formed on the first gate insulating film. A P-type MIS transistor PTr comprises a second gate insulating film 103b which is formed on a second active region 100b in the semiconductor substrate and comprises the insulating material different from that of the first gate insulating film, and a second gate electrode 108b formed on the second gate insulating film. The first gate electrode and the second gate electrode are electrically connected with each other in their upper regions, on an element isolation region, and are disconnected from each other in their lower regions with a sidewall insulating film 105xy therebetween, the sidewall insulating film 105xy being constituted of the same insulating material as that of the first gate insulating film. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：精确地实现由第一MIS晶体管和第二MIS晶体管不同的绝缘材料构成的栅极绝缘膜。解决方案：N型MIS晶体管NTr包括形成在半导体衬底100中的第一有源区域100a上的第一栅极绝缘膜105a和形成在第一栅极绝缘膜上的第一栅电极108a。 P型MIS晶体管PTr包括第二栅极绝缘膜103b，其形成在半导体衬底中的第二有源区域100b上，并且包括与第一栅极绝缘膜的绝缘材料不同的绝缘材料和形成在第一栅极电极108b上的第二栅电极108b 第二栅绝缘膜。第一栅极电极和第二栅电极在其上部区域中在元件隔离区域上彼此电连接，并且在其下部区域中彼此断开，其侧壁绝缘膜105xy之间，侧壁绝缘膜105xy 由与第一栅极绝缘膜相同的绝缘材料构成。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2010040711A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010040711A
公开(公告)日：2010-02-18
申请号：JP2008200880
申请日：2008-08-04
申请人： Panasonic Corp , パナソニック株式会社
发明人： SATO YOSHIHIRO , KAJITANI ATSUHIRO
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/768 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7843
摘要： PROBLEM TO BE SOLVED: To control the deterioration by gate leak in a semiconductor device including n-type and p-type MIS transistors having gate electrodes consisting of metal films with mutually different film thickness. SOLUTION: The semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film 13a formed on a first active area 12a, a first metal film 14a formed on the first gate insulating film 13a and a first gate electrode 24A containing a first silicon film 17a formed on the first metal film 14a. The second MIS transistor includes a second gate insulating film 13b formed on a second active area 12b, a first metal film 14b formed on the second gate insulating film, a second metal film 15b formed on the first metal film 14b and a second gate electrode 24B containing a second silicon film 17b formed on the second metal film 15b. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：为了控制包括n型和p型MIS晶体管的半导体器件中的栅极泄漏的劣化，所述n型和p型MIS晶体管具有由具有相互不同的膜厚度的金属膜组成的栅电极。解决方案：半导体器件包括第一MIS晶体管和第二MIS晶体管。第一MIS晶体管包括形成在第一有源区域12a上的第一栅极绝缘膜13a，形成在第一栅极绝缘膜13a上的第一金属膜14a和形成在第一金属膜上的第一栅极电极24A， 14A。第二MIS晶体管包括形成在第二有源区域12b上的第二栅极绝缘膜13b，形成在第二栅极绝缘膜上的第一金属膜14b，形成在第一金属膜14b上的第二金属膜15b和第二栅极电极24B 含有形成在第二金属膜15b上的第二硅膜17b。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2010010199A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010010199A
公开(公告)日：2010-01-14
申请号：JP2008164603
申请日：2008-06-24
申请人： Panasonic Corp , パナソニック株式会社
发明人： MORI YOSHIHIRO , OGAWA HISASHI , YAMADA TAKAYUKI , SATO YOSHIHIRO
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To overcome the problem that the residue of polysilicon may possibly be left on an element isolation region during fabrication of a semiconductor device having a gate insulating film containing a high dielectric material and a metal gate electrode. SOLUTION: A first transistor of first conductivity type which is equipped with a first gate insulating film 13a, and a first gate electrode 19a having a first underlying conductive film 14a and a first silicon film 18a is formed on the first active region 10a of a semiconductor substrate 10, and a second transistor of second conductivity type which is equipped with a second gate insulating film 13b, and a second gate electrode 19b having a second underlying conductive film 14b and a second silicon film 18b is formed on the second active region 10b of the semiconductor substrate 10. The first gate insulating film 13a contains a high dielectric material and a first metal, the first underlying conductive film 14a contains a conductive material and a first metal, and the second underlying conductive film 14b contains the same conductive material as that of the first underlying conductive film 14a. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了克服在具有含有高电介质材料和金属栅电极的栅极绝缘膜的半导体器件的制造期间，多晶硅残渣可能残留在元件隔离区上的问题。解决方案：在第一有源区10a上形成第一导电类型的第一晶体管，其配备有第一栅极绝缘膜13a和具有第一下导电膜14a和第一硅膜18a的第一栅电极19a 半导体衬底10和第二导电类型的第二晶体管，其配备有第二栅极绝缘膜13b，并且具有第二下部导电膜14b和第二硅膜18b的第二栅极电极19b形成在第二有源层半导体衬底10的区域10b。第一栅极绝缘膜13a包含高电介质材料和第一金属，第一下部导电膜14a包含导电材料和第一金属，并且第二下导电膜14b包含相同的导电材料与第一底层导电膜14a的材料相同。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2009224509A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009224509A
公开(公告)日：2009-10-01
申请号：JP2008066543
申请日：2008-03-14
申请人： Panasonic Corp , パナソニック株式会社
发明人： OSUGA TSUTOMU , SATO YOSHIHIRO , OGAWA HISASHI
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/823462 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device solving the problems such as disconnection of wirings in a PN boundary part and higher resistance, while attaining higher integration in the semiconductor device having an MIPS-structure dual metal gate, and to provide a manufacturing method thereof.
SOLUTION: A gate electrode 122a of an NMIS transistor has a first metal-containing electroconductive film 104a and a third metal-containing electroconductive film 113 formed on the electroconductive film 104a. A PMIS transistor gate electrode 122b has a second metal-containing electroconductive film 104b and a third metal-containing electroconductive film 113 formed on the electroconductive film 104b. The third metal-containing electroconductive film 113 is formed continuously from the first metal-containing electroconductive film 104a onto the second metal-containing electroconductive film 104b, passing above an element-isolation region 102, so that it is in contact with the first and second metal-containing electroconductive films 104a, 104b.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：为了提供解决诸如PN边界部分中的布线断开和更高电阻的问题的半导体器件，同时在具有MIPS结构的双金属栅极的半导体器件中获得更高的集成度，并提供其制造方法。解决方案：NMIS晶体管的栅电极122a具有形成在导电膜104a上的第一含金属的导电膜104a和第三含金属的导电膜113。 PMIS晶体管栅电极122b具有形成在导电膜104b上的第二含金属的导电膜104b和第三含金属的导电膜113。第三含金属的导电膜113从第一含金属的导电膜104a连续地形成在第二含金属的导电膜104b上，通过元件隔离区域102，使得其与第一和第二金属含金属的导电膜104a，104b。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2011017629A Multiaxial acceleration sensor unit 审中-公开
标题翻译：多轴加速传感器单元
公开(公告)号：JP2011017629A
公开(公告)日：2011-01-27
申请号：JP2009162635
申请日：2009-07-09
申请人： Panasonic Corp , パナソニック株式会社
发明人： SATO YOSHIHIRO
IPC分类号： G01P21/00 , G01P15/18
摘要： PROBLEM TO BE SOLVED: To reduce a load applied to a multiaxial acceleration sensor unit in the process for inspecting a detection level, with regard to a method for confirming the detection level in the multiaxial acceleration sensor unit for detecting an acceleration along two orthogonal axes.SOLUTION: The multiaxial acceleration sensor unit uses two orthogonal axes as detection axes 2, 3, and is placed in an eccentric position on a rotating platform 15. While the rotating platform 15 rotates, the biaxial acceleration is detected by using a centrifugal force 16 applied to the multiaxial acceleration sensor unit by a rotation, and an inertial force 17 generated by a change in a rotating speed of the rotation.
摘要翻译：要解决的问题：在用于检测多轴加速度传感器单元中用于检测沿着两个正交轴的加速度的检测水平的方法中，为了减少在检测检测水平的处理中施加于多轴加速度传感器单元的载荷。解决方案：多轴加速度传感器单元使用两个正交轴作为检测轴2,3，并且位于旋转平台15上的偏心位置。当旋转平台15旋转时，通过使用施加的离心力16来检测双轴加速度通过旋转而传递到多轴加速度传感器单元，以及通过旋转的转速的变化而产生的惯性力17。

9. 发明专利

JP2010157587A Semiconductor device, and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010157587A
公开(公告)日：2010-07-15
申请号：JP2008334543
申请日：2008-12-26
申请人： Panasonic Corp , パナソニック株式会社
发明人： OSUGA TSUTOMU , SATO YOSHIHIRO
IPC分类号： H01L21/8238 , H01L21/283 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To solve a problem wherein, in a semiconductor device where two or more transistors of the same conductivity type each having a high-k film and a metal gate electrode are formed in the same substrate, it is difficult to set the difference between threshold voltages larger than the difference between threshold voltages derived from the difference between impurity concentrations in channel regions. SOLUTION: This semiconductor device includes a first transistor, and a second transistor of the same conductivity type as that of the first transistor. The first transistor includes a first gate insulation film 8a containing a high dielectric material and a first metal, and a first gate electrode 11a. The second transistor includes a second gate insulation film 8b containing a high dielectric material, a first metal and impurities for adjusting a threshold voltage, and a second gate electrode 11b. The first gate insulation film 8a is low in concentration of impurities for adjusting a threshold voltage relative to that of the second gate insulation film 8b, or does not contain the impurities for adjusting a threshold voltage. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了解决在同一衬底中形成具有高k膜和金属栅极的相同导电类型的两个或更多个晶体管的半导体器件中的困难的问题，以设置大于由通道区域中的杂质浓度差导出的阈值电压之间的差的阈值电压之间的差。解决方案：该半导体器件包括与第一晶体管相同的导电类型的第一晶体管和第二晶体管。第一晶体管包括含有高电介质材料和第一金属的第一栅极绝缘膜8a和第一栅电极11a。第二晶体管包括含有高电介质材料的第二栅极绝缘膜8b，用于调节阈值电压的第一金属和杂质以及第二栅电极11b。第一栅极绝缘膜8a相对于第二栅极绝缘膜8b调整阈值电压的杂质浓度低，也不含用于调整阈值电压的杂质。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2009224386A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009224386A
公开(公告)日：2009-10-01
申请号：JP2008064435
申请日：2008-03-13
申请人： Panasonic Corp , パナソニック株式会社
发明人： SATO YOSHIHIRO , OGAWA HISASHI
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/336 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： PROBLEM TO BE SOLVED: To obtain high-accuracy formed first and second gate electrodes, and to obtain an element isolation region, having a width which is reduced in the gate breadthwise direction. SOLUTION: A first MIS transistor includes a first gate electrode 30A comprising a second metallic film 30a, formed on a first gate insulation film 13a and an insulation film 27, formed from a side face of the first gate electrode, across the upper surface of a region located sideways of the first gate electrode in a first active region 10a. A second MIS transistor includes a second gate electrode 30B, formed on a second gate insulating film 13b and comprising a first metal film 14b and a conductive film 30b, formed on the first metallic film, and the insulation film 27, formed from a side face of the second gate electrode, across an upper surface of a region located sideways of the second gate electrode in a second active region. The first and second metal films are made of metallic materials which differ from each other, and insulation film is not formed on the upper surfaces of the first and second gate electrodes. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了获得高精度形成的第一和第二栅电极，并获得具有在栅极宽度方向上减小的宽度的元件隔离区域。解决方案：第一MIS晶体管包括第一栅极电极30A，其包括形成在第一栅极绝缘膜13a上的第二金属膜30a和由第一栅电极的侧面形成的绝缘膜27跨过上部在第一有源区域10a中位于第一栅电极侧面的区域的表面。第二MIS晶体管包括形成在第二栅极绝缘膜13b上并且包括形成在第一金属膜上的第一金属膜14b和导电膜30b的第二栅电极30B和由侧面形成的绝缘膜27 的第二栅电极穿过第二有源区域中位于第二栅电极侧面的区域的上表面。第一和第二金属膜由彼此不同的金属材料制成，并且绝缘膜不形成在第一和第二栅电极的上表面上。版权所有（C）2010，JPO＆INPIT

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