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1. 发明专利

JP2006337857A Method for manufacturing semiconductor device, and correction program of chip pattern in semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件中芯片图案的校正程序
公开(公告)号：JP2006337857A
公开(公告)日：2006-12-14
申请号：JP2005164541
申请日：2005-06-03
申请人： Nuflare Technology Inc , Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社ニューフレアテクノロジー , 株式会社東芝
发明人： HONDA NORIYUKI , TSUNAKAWA KIYOSHI , WATANABE SUSUMU , YASHIMA JUN , ABE TAKAYUKI , SUZUKI JUNICHI
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which appropriate correction or transformation can be performed for a divided chip pattern. SOLUTION: The method includes steps of: determining a plurality of computation areas A11, A12 adjacent to each other in a region where chip patterns P29, P30 of a semiconductor device are present on a design plane; forming a computation margin area 59 for each computation area A11 outside and adjacent to the computation area so as to expand the computation area A11 to the computation margin area 59; selecting chip patterns P29, P30 disposed even in a portion in the computation area A11 by each computation area A11, A12; correcting the chip patterns P29, P30 selected in the respective computation areas A11, A12; and fabricating a real pattern on a wafer based on the corrected chip patterns P29b, P30b. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以对分割的芯片图案进行适当的校正或变换的半导体器件的制造方法。解决方案：该方法包括以下步骤：在设计平面上存在半导体器件的芯片图案P29，P30的区域中，确定彼此相邻的多个运算区域A11，A12; 形成计算区域A11的计算边界区域59，将计算区域A11扩展到运算区域59; 选择由计算区域A11，A12设置在计算区域A11的一部分中的芯片图案P29，P30; 校正在各个计算区域A11，A12中选择的芯片图案P29，P30; 以及基于校正的芯片图案P29b，P30b在晶片上制造实际图案。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007057849A Pattern inspection method, exposure mask, and pattern inspection program 审中-公开
标题翻译：模式检验方法，曝光掩模和图案检测程序
公开(公告)号：JP2007057849A
公开(公告)日：2007-03-08
申请号：JP2005243363
申请日：2005-08-24
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HONDA NORIYUKI , MIYAMOTO HIROE , YAMAGUCHI NORIKO
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F1/84 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a pattern inspection method for efficiently performing lithography rule check on a design pattern after optical proximity correction.
SOLUTION: The method includes: a first step (S01 to S03) of subjecting a cell pattern preliminarily registered in a cell library to optical proximity correction (OPC) subjecting the pattern after the OPC to lithography rule checking (LRC) and registering a cell having the pattern passing the LRC in a data base; a second step (S05, S06) of identifying a cell from a design pattern after OPC, the cell which is equal to a cell registered in the data base by referring to the data base; a third step (S07, S08) of extracting an object pattern for the LRC from the design pattern after OPC based on the outer shape of the identified cell; and a fourth step (S09) of subjecting the object pattern for LRC to LRC.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在光学邻近校正之后有效执行设计图案的光刻规则检查的图案检查方法。解决方案：该方法包括：对预先登记在单元库中的单元图案进行光学接近校正（OPC）的OPC（OPC）之后的第一步骤（S01至S03），使OPC之后的图案经受光刻规则检查（LRC）并记录具有通过数据库中的LRC的图案的单元; 从OPC之后的设计模式识别单元的第二步骤（S05，S06），通过参考数据库等同于在数据库中登记的单元的单元; 基于所识别的单元的外形，从OPC之后的设计图案中提取LRC的对象图案的第三步骤（S07，S08）以及对LRC的目标图案进行LRC的第四步骤（S09）。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2003282487A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2003282487A
公开(公告)日：2003-10-03
申请号：JP2002078703
申请日：2002-03-20
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： TSUCHIYA IKUO , HONDA NORIYUKI
IPC分类号： H01L21/822 , H01L21/301 , H01L21/56 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To address the problem how to achieve reduction in occupancy areas of semiconductor chips as well as to prevent cracks generated in protective films when the semiconductor chips are cut to be separated. SOLUTION: The present invention provides a structure where slits 5 are formed in the protective films of the semiconductor chips 1 so as not to face monitor element terminal openings 3 formed in dicing lines 2. COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：为了解决如何实现半导体芯片的占用面积的减少以及当半导体芯片被切割分离时防止在保护膜中产生的裂纹的问题。解决方案：本发明提供一种结构，其中在半导体芯片1的保护膜中形成狭缝5，以便不面对形成在切割线2中的监视元件端子开口3.版权所有（C）2004 ，JPO

4. 发明专利

JP2005136102A Yield estimation system and its method for semiconductor device 审中-公开
标题翻译： YIELD估算系统及其半导体器件的方法
公开(公告)号：JP2005136102A
公开(公告)日：2005-05-26
申请号：JP2003369570
申请日：2003-10-29
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： NASU ISATO , HONDA NORIYUKI , MIYAMOTO HIROE , HAYAKAWA MASAYUKI
IPC分类号： G01R31/02 , H01L21/02 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide an yield estimation system and its method which can calculate an yield of a semiconductor device passing through a final process of in-line processing, accurately and in a shorter time than in a conventional method and a system.
SOLUTION: The yield estimation system comprises a pattern recognition processor 63 and a data calculator 60. The pattern recognition processor 63 reads out the diameter value of a defective model from a defective model data storing section 59, then reads out interconnection layout data having a line width nor larger than the diameter value of the defective model, creates a figure of a candidate for a defective portion, and stores the graphic data of the candidate for a defective portion, including an area value of the figure of the candidate for a defective portion into a candidate-for-defective-portion data storing section 58. The data calculator 60 reads out the graphic data about the candidate for a defective portion which is stored in the candidate-for-defective-portion data storing section 58 and the graphic data about the figure of the defective model stored in a defective model scatter diagram database 56, calculates the probability that the figure of the candidate for a defective portion and the figure of the defective model overlap with each other, and then stores its result as an yield calculation result about the semiconductor device into an yield estimated data storing section 62.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种屈服估计系统及其方法，其可以比传统方法和传统方法中准确地和在更短的时间内计算通过在线处理的最终过程的半导体器件的产量，系统。产量估计系统包括模式识别处理器63和数据计算器60.模式识别处理器63从缺陷模型数据存储部分59中读出缺陷模型的直径值，然后读出互连布局数据具有不大于缺陷模型的直径值的线宽度，创建缺陷部分的候选者的图形，并且存储缺陷部分的候选者的图形数据，包括候选对象的图形的面积值，缺陷部分变成缺陷部分数据存储部分58.数据计算器60读出关于存储在缺陷部分数据存储部分58中的缺陷部分的候选的图形数据，以及关于存储在有缺陷的模型散点图数据库56中的缺陷模型的图形的图形数据计算出一个失败的候选人的数字的概率故障模型的图形和缺陷模型的图形彼此重叠，然后将其结果作为关于半导体器件的收益计算结果存储到收益估计数据存储部分62中。（C）2005，JPO＆NCIPI

5. 发明专利

JP2009169680A Database creation method, database device and design data evaluation method 有权
标题翻译：数据库创建方法，数据库设备和设计数据评估方法
公开(公告)号：JP2009169680A
公开(公告)日：2009-07-30
申请号：JP2008007165
申请日：2008-01-16
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MAEDA YUKITO , HONDA NORIYUKI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045
摘要： PROBLEM TO BE SOLVED: To provide a database creation method for suppressing the increase of time required for evaluating the design data of a semiconductor integrated circuit.
SOLUTION: This database creation method configured by registering a plurality of functional block cells configuring design data of a plurality of semiconductor circuits and a plurality of evaluation values for the plurality of functional blocks in association with each other includes: (S1) determining whether or not a plurality of cells Cij configuring the design data are registered in the database 4 concerning the design data of a desired semiconductor integrated circuit; (S2) when it is determined that any cell Cij which has not been registered in the database 4 is present among the plurality of cells Cij configuring the design data of the desired semiconductor integrated circuit, calculating the evaluation values of the unregistered cells; and (S3) updating the database 4 by registering the unregistered cells and the evaluation values in the database 4 in association with each other.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种数据库创建方法，用于抑制用于评估半导体集成电路的设计数据所需的时间的增加。解决方案：通过将配置多个半导体电路的设计数据的多个功能块单元和多个功能块的多个评估值相互关联而配置的数据库生成方法包括：（S1）确定构成设计数据的多个单元Cij是否登记在关于期望的半导体集成电路的设计数据的数据库4中; （S2）当确定在配置所需半导体集成电路的设计数据的多个单元Cij中存在尚未登记在数据库4中的任何单元Cij时，计算未注册单元的评估值; 和（S3）通过将未注册的单元和评估值相关联地注册在数据库4中来更新数据库4。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2006323023A METHOD FOR FORMING MASK PATTERN 审中-公开
公开(公告)号：JP2006323023A
公开(公告)日：2006-11-30
申请号：JP2005144650
申请日：2005-05-17
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP , NUFLARE TECHNOLOGY INC
发明人： HONDA NORIYUKI , TSUNAKAWA KIYOSHI , WATANABE SUSUMU , YASHIMA JUN , ABE TAKAYUKI , SUZUKI JUNICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F7/20 , G06F17/50 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a mask pattern, with which increase in a time period for drawing is suppressed and improvement of accuracy in drawing is possible. SOLUTION: A layout data of the mask pattern is acquired, and a first correction map, in which first dimensional correction amounts are respectively set to a plurality of first small regions formed by partitioning the mask pattern arrangement surface in a grid, is formed based on the arrangement of the mask pattern. A second correction map, in which second dimensional correction amounts are respectively set to a plurality of second small regions partitioned in the same grid shape as that of the plurality of first small regions and displaced relative to the first small regions, is formed based on the arrangement of the mask pattern. Then the mask pattern is corrected based on the first and the second correction maps. COPYRIGHT: (C)2007,JPO&INPIT

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