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1. 发明专利

JP2006323023A METHOD FOR FORMING MASK PATTERN 审中-公开
公开(公告)号：JP2006323023A
公开(公告)日：2006-11-30
申请号：JP2005144650
申请日：2005-05-17
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP , NUFLARE TECHNOLOGY INC
发明人： HONDA NORIYUKI , TSUNAKAWA KIYOSHI , WATANABE SUSUMU , YASHIMA JUN , ABE TAKAYUKI , SUZUKI JUNICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F7/20 , G06F17/50 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a mask pattern, with which increase in a time period for drawing is suppressed and improvement of accuracy in drawing is possible. SOLUTION: A layout data of the mask pattern is acquired, and a first correction map, in which first dimensional correction amounts are respectively set to a plurality of first small regions formed by partitioning the mask pattern arrangement surface in a grid, is formed based on the arrangement of the mask pattern. A second correction map, in which second dimensional correction amounts are respectively set to a plurality of second small regions partitioned in the same grid shape as that of the plurality of first small regions and displaced relative to the first small regions, is formed based on the arrangement of the mask pattern. Then the mask pattern is corrected based on the first and the second correction maps. COPYRIGHT: (C)2007,JPO&INPIT

2. 发明专利

JP2006337857A Method for manufacturing semiconductor device, and correction program of chip pattern in semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件中芯片图案的校正程序
公开(公告)号：JP2006337857A
公开(公告)日：2006-12-14
申请号：JP2005164541
申请日：2005-06-03
申请人： Nuflare Technology Inc , Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社ニューフレアテクノロジー , 株式会社東芝
发明人： HONDA NORIYUKI , TSUNAKAWA KIYOSHI , WATANABE SUSUMU , YASHIMA JUN , ABE TAKAYUKI , SUZUKI JUNICHI
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which appropriate correction or transformation can be performed for a divided chip pattern. SOLUTION: The method includes steps of: determining a plurality of computation areas A11, A12 adjacent to each other in a region where chip patterns P29, P30 of a semiconductor device are present on a design plane; forming a computation margin area 59 for each computation area A11 outside and adjacent to the computation area so as to expand the computation area A11 to the computation margin area 59; selecting chip patterns P29, P30 disposed even in a portion in the computation area A11 by each computation area A11, A12; correcting the chip patterns P29, P30 selected in the respective computation areas A11, A12; and fabricating a real pattern on a wafer based on the corrected chip patterns P29b, P30b. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以对分割的芯片图案进行适当的校正或变换的半导体器件的制造方法。解决方案：该方法包括以下步骤：在设计平面上存在半导体器件的芯片图案P29，P30的区域中，确定彼此相邻的多个运算区域A11，A12; 形成计算区域A11的计算边界区域59，将计算区域A11扩展到运算区域59; 选择由计算区域A11，A12设置在计算区域A11的一部分中的芯片图案P29，P30; 校正在各个计算区域A11，A12中选择的芯片图案P29，P30; 以及基于校正的芯片图案P29b，P30b在晶片上制造实际图案。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JPH1117025A THREE TRANSISTOR TYPE DYNAMIC RAM MEMORY CELL 失效
公开(公告)号：JPH1117025A
公开(公告)日：1999-01-22
申请号：JP16889597
申请日：1997-06-25
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： KIMURA MASAHIRO , TANAKA YUTAKA , ABE TAKAYUKI , OGAWA KYOSUKE , KOBAYASHI TOSHIHIRO
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To reduce the area of memory cells by regulating a cell pattern in such a manner that a channel length of a MOS transistor for storing charges and driving read data lines is made smaller than the width across which a gate overlaps a transistor region. SOLUTION: A gate polysilicon 3 is arranged on a transistor region 1 through an insulating film such as an oxide film, the region 1 being formed on a silicon substrate. Then, the shape of the polysilicon 3 is regulated in such a manner that a gate region that is an overlap 9 between the polysilicon 3 and the region 1 is formed of a dimensionally narrow portion A and a wide portion excluding the narrow portion from the gate region 9. When a predetermined high voltage is applied to the thus regulated polysilicon 3, a channel is formed, and electrons are caused to flow from a source region 5 to a drain region 7 via such channel to establish continuity.

4. 发明专利

JP2001273780A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001273780A
公开(公告)日：2001-10-05
申请号：JP2000088407
申请日：2000-03-28
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： SUZUKI TOMOAKI , HERAI TSUTOMU , KAWASAKI SOICHI , ABE TAKAYUKI , MORI TOSHIAKI , NISHIMAKI HARUYOSHI
IPC分类号： G11C14/00 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a DRAM having a DRAM core circuit incorporating a ROM function by which desired fixed data stored in a chip can be written in a DRAM cell simply and at high speed. SOLUTION: This circuit is provided with a DRAM cell 20 which can switch a logic value of a stored data to '1' or '0' any time, a ROM cell 21 which can fix a logic value of stored data to '1' or '0' continuously, and a DRAM cell with ROM function provided with a switch element 22 controlled by a control signal INIT and transferring a stored data of the ROM cell to the DRAM cell.

5. 发明专利

JPH11214537A SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH11214537A
公开(公告)日：1999-08-06
申请号：JP1707798
申请日：1998-01-29
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： ABE TAKAYUKI , TANAKA YUTAKA , OGAWA KYOSUKE , KIMURA MASAHIRO , KOBAYASHI TOSHIHIRO
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent fluctuation of the characteristics of transistors due to fluctuation of a process and a malfunction when the transistors connected to a bit line are formed in an opposite pattern, 180 degrees in terms of the property of a circuit between the side of a memory cell and that of a dummy cell. SOLUTION: A bit line WB where the date of a dummy cell DC are read crosses a bit line RB where the data of a memory cell MC are read, and the circuit pattern of a transistor MT1 connected to the bit line RB at the side of the memory cell MC and the circuit pattern of a transistor DT1 that is connected to the bit line WB at the side of the dummy cell DC are formed in the same direction, thus enabling the characteristics of the transistor DT1 and the transistor MT1 to fluctuate in-phase even when the pattern deviates by the fluctuation of a process and hence preventing a malfunction from occurring.

6. 发明专利

JPH1116344A 3-TRANSISTOR DRAM MEMORY DEVICE 失效
公开(公告)号：JPH1116344A
公开(公告)日：1999-01-22
申请号：JP16890497
申请日：1997-06-25
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： OGAWA KYOSUKE , TANAKA YUTAKA , ABE TAKAYUKI , KIMURA MASAHIRO , KOBAYASHI TOSHIHIRO
IPC分类号： G11C11/405 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent a through current and reduce power consumption by setting the number of data read nodes and data write nodes of a memory cell connected to one data line of the data line pair equal to the number of data read nodes and data write nodes of the memory cell connected to the other data line. SOLUTION: A pair of data lines B00, B01 of the same column are connected to one differential amplifier and two MOS transistors for write switch and two MOS transistors for read switch are respectively connected to the data lines B00, B01. A memory cell is arranged so that the MOS transistor for write switch and MOS transistor for read switch are alternately connected to one data line to reduce the area of memory array. Moreover, a through current preventing circuit 31 prevents generation of a through current flowing between the power source voltage and grounding voltage during the write and read operation to the memory cell.

7. 发明专利

JPH11162164A DRAM AND 3-TRANSISTOR TYPE DRAM 失效
公开(公告)号：JPH11162164A
公开(公告)日：1999-06-18
申请号：JP32486397
申请日：1997-11-26
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： KOBAYASHI TOSHIHIRO , TANAKA YUTAKA , ABE TAKAYUKI , OGAWA KYOSUKE , KIMURA MASAHIRO
IPC分类号： G11C11/405 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To use the single power supply of a device as an initial voltage of a dummy cell by delaying a timing when the dummy cell opens as compared with the timing when a memory cell opens by a specific amount of time and by constituting the dummy cell in the same dimension as the memory cell. SOLUTION: In a memory cell array 1, a 3-transistor-type memory cell 14 for storing 1 or 0 is connected to each intersecting part between a plurality of bit pairs and word lines. Further, a dummy cell 15 is connected to each intersecting part between each pair of bit line 11-1a, 11-1b... and a dummy read word line 13. A diffusion resistor 16 is inserted into the dummy read word line 13. By selecting the resistance of the diffusion resistor 16 so that the read bit line of the dummy cell 15 reaches a potential at the middle of L and H levels, a timing when the dummy cell opens can be delayed from that when the memory cell opens.

8. 发明专利

JP2012212793A Method of manufacturing semiconductor device, lithography apparatus, program and pattern transfer device 有权
标题翻译：制造半导体器件的方法，光刻设备，程序和图案传输器件
公开(公告)号：JP2012212793A
公开(公告)日：2012-11-01
申请号：JP2011077811
申请日：2011-03-31
申请人： Nuflare Technology Inc , 株式会社ニューフレアテクノロジー
发明人： ABE TAKAYUKI
IPC分类号： H01L21/027
CPC分类号： G03F7/70616 , G03F1/36 , G03F1/50 , G03F1/68 , G03F1/70 , G03F1/78 , G03F7/20 , G03F7/2063 , H01L21/3086
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that can further reduce a dimensional error of a pattern to be finally transferred onto a semiconductor substrate.SOLUTION: A method of manufacturing a semiconductor device comprises a step (S102) for dividing, into plural small areas, a pattern area of a desired pattern which is scheduled to be formed on a semiconductor substrate, a step (S104 to S109) for obtaining a combination of the shape of irradiation light for transfer whose pattern dimensional error is smaller every small area, and the pattern shape of a mask pattern obtained by correcting a partial pattern that is formed on the mask for transfer and represents the small area concerned out of the desired pattern, a step (S120, S122) for sequentially performing multiple exposure to the partial pattern in all the divided small area by transferring the mask pattern onto the semiconductor substrate with irradiation light having the combined shape every small area, and a step (S126) for forming the desired pattern on the semiconductor substrate which has been subjected to multiple exposure.
摘要翻译：解决的问题：提供一种制造半导体器件的方法，该半导体器件可以进一步减少最终转印到半导体衬底上的图案的尺寸误差。解决方案：制造半导体器件的方法包括步骤（S102），用于将预定形成在半导体衬底上的期望图案的图案区域分成多个小区域，步骤（S104至S109）），用于获得图案尺寸误差小于每个小面积的用于转印的照射光的形状的组合，以及通过校正形成在转印用掩模上的部分图案而获得的掩模图案的图案形状，并且表示小区域涉及所需图案的步骤（S120，S122），用于通过以每小面积组合形状的照射光将掩模图案转印到半导体基板上，在所有分割的小区域中顺序地对部分图案进行多次曝光;以及用于在经过多次曝光的半导体衬底上形成所需图案的步骤（S126）。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2012182506A Pattern generation method and charged particle beam-drawing apparatus 有权
标题翻译：图案生成方法和充电颗粒光束装置
公开(公告)号：JP2012182506A
公开(公告)日：2012-09-20
申请号：JP2012145539
申请日：2012-06-28
申请人： Nuflare Technology Inc , 株式会社ニューフレアテクノロジー
发明人： EMI KEIKO , SUZUKI JUNICHI , ABE TAKAYUKI
IPC分类号： H01L21/027 , G03F7/20 , H01J37/305
摘要： PROBLEM TO BE SOLVED: To provide a pattern generation method and an apparatus for reducing a correction residual in loading effect correction.SOLUTION: A pattern generation method, in one aspect of the present invention, for forming a pattern on a sample 10, comprises: changing a dimension of a design pattern 12 by using an area S of the pattern included in each mesh-like region and a total sum of length of outer circumferential sides of the pattern in a pattern forming region of the sample 10 which is virtually divided into a plurality of the mesh-like regions; and correcting a dimension error of the pattern caused by loading effects. By the present invention, a correction residual in the loading effect correction can be reduced.
摘要翻译：要解决的问题：提供一种用于减小加载效应校正中的校正残差的图案生成方法和装置。解决方案：在本发明的一个方面，用于在样品10上形成图案的图案生成方法包括：通过使用包含在每个网格图案中的图案的面积S来改变设计图案12的尺寸，在样品10的图案形成区域中，图案的外周侧的长度的总和实质上分为多个网状区域; 并校正由加载效应引起的图案的尺寸误差。通过本发明，可以减少装载效果校正中的校正残差。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2010161415A Charged particle beam drawing method and apparatus of the same 审中-公开
标题翻译：充电颗粒光束绘图方法及其设备
公开(公告)号：JP2010161415A
公开(公告)日：2010-07-22
申请号：JP2010088368
申请日：2010-04-07
申请人： Nuflare Technology Inc , 株式会社ニューフレアテクノロジー
发明人： ABE TAKAYUKI , YASHIMA JUN
IPC分类号： H01L21/027 , H01J37/147 , H01J37/305
CPC分类号： H01J37/147 , B82Y10/00 , B82Y40/00 , G03F1/78 , H01J37/045 , H01J37/24 , H01J37/3023 , H01J37/3174 , H01J2237/0432 , H01J2237/1504 , H01J2237/30472
摘要： PROBLEM TO BE SOLVED: To provide a method and an apparatus for further shortening a drawing time. SOLUTION: This drawing apparatus 100 includes: a BLK deflector 212 configured to cause an electrode beam 200 to pass therethrough without being deflected to turn on the beam, and turn off the beam by being deflected; a shaping deflector 205 configured to deflect and shape the electron beam 200; and an object deflector 208 configured to deflect the electron beam 200 to a predetermined position of a sample 101. At least two of the deflectors control the electron beams 200 of different shots at the same time so as to be deflective. According to one embodiment, the next shot is emitted early, whereby a drawing time is reduced accordingly. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种进一步缩短绘制时间的方法和装置。解决方案：该绘图装置100包括：BLK偏转器212，其被配置为使电极束200穿过其中而不被偏转以接通光束，并且通过偏转来关闭光束; 构造成使电子束200偏转和成形的成形偏转器205; 以及被配置为将电子束200偏转到样品101的预定位置的物体偏转器208.至少两个偏转器同时控制不同镜头的电子束200以便偏转。根据一个实施例，下一个镜头被提前发射，从而相应地减小了绘制时间。版权所有（C）2010，JPO＆INPIT

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