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1. 发明专利

JP2008052221A Pattern generating method and program 审中-公开
标题翻译：模式生成方法和程序
公开(公告)号：JP2008052221A
公开(公告)日：2008-03-06
申请号：JP2006231142
申请日：2006-08-28
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MAEDA YUKITO , OYOSHI KOJIRO
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/82
CPC分类号： G03F1/36 , G03F1/70
摘要： PROBLEM TO BE SOLVED: To provide a pattern generating method by which a pattern eliminating a defective portion can be obtained without consuming much time. SOLUTION: The method includes: a step ST16 of setting data of a first pattern, a second pattern obtained by applying predetermined processing to the first pattern, and a defective portion based on the second pattern; a step S17 of defining a correction region including the defective portion; a step ST18 of selecting a correction method corresponding to the kind of the defective portion; a step ST19 of generating a correction object pattern on the basis of the first pattern and the correction region; the step ST19 of generating a correction reference pattern on the basis of the second pattern and the correction region; a step ST21 of correcting the correction object pattern by the selected correction method on the basis of the correction object pattern and the correction reference pattern; and a step ST23 of deciding whether a defective portion based on the corrected correction object pattern is present or not in the correction region or its peripheral region. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种图案生成方法，通过该方法可以获得消除缺陷部分的图案而不花费大量的时间。解决方案：该方法包括：设置第一图案的数据的步骤ST16，通过对第一图案应用预定处理获得的第二图案和基于第二图案的缺陷部分; 限定包括缺陷部分的校正区域的步骤S17; 选择对应于该缺陷部分的种类的校正方法的步骤ST18; 基于第一图案和校正区域生成校正对象图案的步骤ST19; 基于第二图案和校正区域生成校正参考图案的步骤ST19; 基于校正对象图案和校正基准图案，通过所选择的校正方法校正校正对象图案的步骤ST21; 以及在校正区域或其周边区域中判定是否存在基于校正校正对象图案的缺陷部分的步骤ST23。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2009169680A Database creation method, database device and design data evaluation method 有权
标题翻译：数据库创建方法，数据库设备和设计数据评估方法
公开(公告)号：JP2009169680A
公开(公告)日：2009-07-30
申请号：JP2008007165
申请日：2008-01-16
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MAEDA YUKITO , HONDA NORIYUKI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045
摘要： PROBLEM TO BE SOLVED: To provide a database creation method for suppressing the increase of time required for evaluating the design data of a semiconductor integrated circuit.
SOLUTION: This database creation method configured by registering a plurality of functional block cells configuring design data of a plurality of semiconductor circuits and a plurality of evaluation values for the plurality of functional blocks in association with each other includes: (S1) determining whether or not a plurality of cells Cij configuring the design data are registered in the database 4 concerning the design data of a desired semiconductor integrated circuit; (S2) when it is determined that any cell Cij which has not been registered in the database 4 is present among the plurality of cells Cij configuring the design data of the desired semiconductor integrated circuit, calculating the evaluation values of the unregistered cells; and (S3) updating the database 4 by registering the unregistered cells and the evaluation values in the database 4 in association with each other.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种数据库创建方法，用于抑制用于评估半导体集成电路的设计数据所需的时间的增加。解决方案：通过将配置多个半导体电路的设计数据的多个功能块单元和多个功能块的多个评估值相互关联而配置的数据库生成方法包括：（S1）确定构成设计数据的多个单元Cij是否登记在关于期望的半导体集成电路的设计数据的数据库4中; （S2）当确定在配置所需半导体集成电路的设计数据的多个单元Cij中存在尚未登记在数据库4中的任何单元Cij时，计算未注册单元的评估值; 和（S3）通过将未注册的单元和评估值相关联地注册在数据库4中来更新数据库4。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2005316135A Design correction method, design pattern generating method, and process proximity correction method 审中-公开
标题翻译：设计校正方法，设计图案生成方法和过程逼近校正方法
公开(公告)号：JP2005316135A
公开(公告)日：2005-11-10
申请号：JP2004134011
申请日：2004-04-28
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： KOTANI TOSHIYA , NOJIMA SHIGEKI , MAEDA YUKITO
IPC分类号： G03C5/00 , G03F1/36 , G03F1/68 , G03F9/00 , G06F17/50 , H01L21/027 , G03F1/08
CPC分类号： G03F1/36
摘要： PROBLEM TO BE SOLVED: To finish the corner of a pattern as a desired pattern, and to improve the pattern accuracy.
SOLUTION: The design pattern correction method to apply a correction, to avoid the influence of a minute step-like figure to a design pattern to form a desired planar pattern figure on a wafer includes: extracting edges QP, QR forming the vertex Q of a design pattern 31; measuring the length of the extracted edges QP, QR; deciding whether the length of the edges QP, QR is shorter than a predetermined length; extracting two vertexes P, R connected to the edges QP, QR when the length of the edges QP, QR is decided to be shorter than the predetermined length; and deforming the design pattern, to make the extracted two vertexes P, R coincide with each other.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：将图案的一角完成为所需图案，并提高图案精度。解决方案：用于应用校正的设计图案校正方法，以避免微小阶梯状图对设计图案的影响以在晶片上形成期望的平面图案图形包括：提取边缘QP，QR形成顶点设计图案31的Q; 测量提取的边缘的长度QP，QR; 确定边缘QP，QR的长度是否短于预定长度; 当边缘QP，QR的长度被确定为短于预定长度时，提取连接到边缘QP，QR的两个顶点P，R; 并使设计图案变形，使提取的两个顶点P，R彼此一致。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005250360A Verification apparatus and verification method for mask pattern 审中-公开
标题翻译：掩模图案的验证装置和验证方法
公开(公告)号：JP2005250360A
公开(公告)日：2005-09-15
申请号：JP2004064221
申请日：2004-03-08
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： MAEDA YUKITO
IPC分类号： G03F1/36 , G03F1/68 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To provide a verification apparatus and a verification method for a mask pattern by which a portion where conventionally OPC verification fails can be detected by devising procedures of dividing edges or setting simulation points for the OPC verification and high accuracy OPC verification can be performed.
SOLUTION: The invention presents a verification apparatus and a verification method for a mask pattern to be used for the manufacture of a semiconductor integrated circuit. The apparatus is equipped with a segment extracting unit 112 which includes: an edge dividing means 112b to more finely divide each line of the mask pattern to be verified according to a designated division system and a division parameter than in the OPC process; and a simulation point disposing means 112c to dispose a simulation point on each divided segment by a designated system.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于掩模图案的验证装置和验证方法，通过该掩模图案可以通过设计用于OPC验证的分割边缘的程序或设置模拟点来检测传统的OPC验证失败的部分，并且具有高精度可以执行OPC验证。解决方案：本发明提出了一种用于制造半导体集成电路的掩模图案的验证装置和验证方法。该装置配备有片段提取单元112，其包括：边缘分割装置112b，根据指定的分割系统和除OPC过程之外的分割参数，更细地细分待验证的掩模图案的每一行; 以及模拟点设置装置112c，用于通过指定的系统在每个划分的段上设置模拟点。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2014072420A Creation method of mask data and manufacturing method of integrated circuit device 有权
标题翻译：掩模数据的创建方法和集成电路设备的制造方法
公开(公告)号：JP2014072420A
公开(公告)日：2014-04-21
申请号：JP2012218043
申请日：2012-09-28
申请人： Toshiba Corp , 株式会社東芝
发明人： MAEDA YUKITO , ITO SHINICHI
IPC分类号： H01L21/3205 , G03F1/00 , H01L21/027 , H01L21/768 , H01L23/522
CPC分类号： H01L21/027 , G03F1/144 , G03F1/36 , G06F17/5068
摘要： PROBLEM TO BE SOLVED: To provide a creation method of mask data for manufacturing an integrated circuit by using DSA technique, and to provide a manufacturing method of an integrated circuit device.SOLUTION: A creation method of mask data for forming a circuit pattern on a substrate by using an induction self-organization material comprises: a step of extracting a first region existing in an initial pattern including a plurality of wiring patterns extending in a first direction, but not existing in the circuit pattern; a step of setting a second region by stretching the first region in a second direction crossing the first direction, so as to straddle the first region in the second direction; and a third step of setting a third region including one or more second region, and in which the induction self-organization material is disposed.
摘要翻译：要解决的问题：提供通过使用DSA技术制造集成电路的掩模数据的创建方法，并提供集成电路器件的制造方法。解决方案：一种用于在电路图案上形成电路图案的掩模数据的创建方法通过使用感应自组织材料的衬底包括：提取存在于包括沿着第一方向延伸但不存在于电路图案中的多个布线图案的初始图案的第一区域的步骤; 通过沿与第一方向交叉的第二方向拉伸第一区域来设置第二区域的步骤，以沿第二方向跨越第一区域; 以及第三步骤，设置包括一个或多个第二区域的第三区域，并且其中设置所述感应自组织材料。

6. 发明专利

JP2007121549A Method for correcting pattern and program therefor 审中-公开
标题翻译：校正图案及其程序的方法
公开(公告)号：JP2007121549A
公开(公告)日：2007-05-17
申请号：JP2005311576
申请日：2005-10-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MAEDA YUKITO , OGAWA RYUJI
IPC分类号： G03F1/68 , G03F1/70
摘要： PROBLEM TO BE SOLVED: To provide a method for correcting a pattern with which an appropriate correction value can be set for a pattern. SOLUTION: From one of the design data of an integrated circuit device and the data prepared by graphic processing of the design data, a side of a pattern is divided into a plurality of portions (S11) and the width of the pattern corresponding to the side and the distance between the pattern and the adjacent pattern at a plurality of points in each divided side are measured (S12) a plurality of moving distances are extracted from a correction table based on the pattern width and the distance to the adjacent pattern measured at a plurality of measuring points (S13) and a correction value of the divided side is calculated based on the extracted plurality of moving distances (S14). The pattern is corrected based on the calculated correction value (S15). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于校正可以为图案设置适当的校正值的图案的方法。解决方案：从集成电路器件的设计数据和通过设计数据的图形处理准备的数据之一，将图案的一侧划分为多个部分（S11），并且对应的图案的宽度测量各分割侧的多个点处的图案与相邻图案之间的距离（S12），基于图案宽度和与相邻图案的距离，从校正表中提取多个移动距离在多个测量点处测量（S13），并且基于所提取的多个移动距离来计算分割侧的校正值（S14）。基于所计算的校正值校正图案（S15）。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2014053494A Patterning method 有权
标题翻译：绘图方法
公开(公告)号：JP2014053494A
公开(公告)日：2014-03-20
申请号：JP2012197782
申请日：2012-09-07
申请人： Toshiba Corp , 株式会社東芝
发明人： MAEDA YUKITO , MOTOI TAKASHI
IPC分类号： H01L21/027
CPC分类号： H01L21/02318 , B81C1/00031 , B81C2201/0149 , H01L21/0271 , H01L21/32139
摘要： PROBLEM TO BE SOLVED: To provide a patterning method which allows for formation of a pattern on a substrate corresponding to a pattern after phase separation in a different size, a shape or a pitch, with a small number of steps.SOLUTION: In a patterning method, first and second guide patterns for subjecting a DSA material to induction self-organization are formed on a processed film on a substrate. Under first DSA conditions, a first pattern after phase separation having regularity for the first guide pattern is formed, and a first pattern on the substrate is formed by processing the processed film on the lower layer side of the first pattern after phase separation. Thereafter, under second DSA conditions, a second pattern after phase separation having regularity for the second guide pattern is formed, and a second pattern on the substrate is formed by processing the processed film on the lower layer side of the second pattern after phase separation.
摘要翻译：要解决的问题：提供一种图案化方法，其允许在相同于相分离之后的图案的基板上以不同的尺寸，形状或间距，以少量的步骤形成图案。图案化：在图案化在基板上的处理膜上形成用于使DSA材料进行感应自组织的第一和第二引导图案。在第一DSA条件下，形成具有第一引导图案的规则性的相分离后的第一图案，并且通过在相分离后在第一图案的下层侧处理经处理的膜而在基板上形成第一图案。此后，在第二DSA条件下，形成具有第二引导图案的规则性的相分离后的第二图案，并且通过在相分离之后对第二图案的下层侧的处理膜进行处理来形成基板上的第二图案。

8. 发明专利

JP2010079184A Generating method for pattern data, and pattern data generating program 有权
标题翻译：模式数据生成方法和模式数据生成程序
公开(公告)号：JP2010079184A
公开(公告)日：2010-04-08
申请号：JP2008250293
申请日：2008-09-29
申请人： Toshiba Corp , 株式会社東芝
发明人： OGAWA RYUJI , MIYAIRI MASAHIRO , MAEDA YUKITO , KYO SUIGEN , TANAKA SATOSHI
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50
CPC分类号： G03F1/36
摘要： PROBLEM TO BE SOLVED: To provide a generating method for pattern data in which occurrence of a fatal error is suppressed when a semiconductor manufacturing process is implemented based upon a cell pattern to be evaluated. SOLUTION: A first simulation result is obtained by performing process simulation on mask pattern data based upon the cell pattern to be evaluated on data to be evaluated, a marginal error pattern in the cell pattern to be evaluated is extracted from the result, and a cell to be evaluated with a peripheral environmental pattern which has a peripheral environment pattern disposed on the marginal error pattern so that a second simulation result obtained by generating the mask pattern data and performing the process simulation becomes worse than the first simulation result is generated. Process simulation is performed on mask pattern data based upon the cell pattern to be evaluated with the peripheral environment pattern and if there is a fatal error pattern, the cell pattern to be evaluated including the marginal error pattern or the mask pattern data based upon the cell to be evaluated is corrected. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种当基于要评估的单元图案来实现半导体制造处理时抑制致命错误的发生的图形数据的生成方法。解决方案：通过基于要评估的数据要评估的单元格图案对掩模图案数据进行处理模拟来获得第一模拟结果，从结果中提取要评估的单元格图案中的边缘误差图案，以及周边环境模式进行评估的单元，其具有设置在边缘误差图案上的周边环境图案，从而生成通过生成掩模图案数据并进行处理模拟而获得的第二模拟结果变得比第一模拟结果更差。基于要利用外围环境模式评估的单元图案对掩模图案数据执行过程模拟，并且如果存在致命错误模式，则基于该单元的待评估的单元图案包括边缘误差图案或掩模图案数据被评估被更正。（C）2010，JPO＆INPIT

9. 发明专利

JP2009181053A Method and program for preparing evaluation pattern 审中-公开
标题翻译：用于准备评估模式的方法和程序
公开(公告)号：JP2009181053A
公开(公告)日：2009-08-13
申请号：JP2008021558
申请日：2008-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： MAEDA YUKITO , OGAWA RYUJI , KYO SUIGEN , TANAKA SATOSHI
IPC分类号： G03F1/36 , G03F1/68
摘要： PROBLEM TO BE SOLVED: To provide a method and program for preparing an evaluation pattern, which can appropriately evaluate pattern transfer fidelity. SOLUTION: The method for preparing a pattern includes: a step of inspecting the pattern transfer fidelity of an object to be inspected for each peripheral candidate pattern, wherein a plurality of the marginal candidate patterns are arranged on a periphery of the object to be inspected; a step of extracting at least one peripheral pattern from among the plurality of the marginal candidate patterns based on the inspection results; and a step of preparing the evaluation pattern by arranging the peripheral patterns on the periphery of the object to be evaluated. COPYRIGHT: (C)2009,JPO&INPIT

10. 发明专利

JP2012042498A Method for forming mask pattern and method for forming lithography target pattern 审中-公开
标题翻译：形成掩模图案的方法和形成图形目标图案的方法
公开(公告)号：JP2012042498A
公开(公告)日：2012-03-01
申请号：JP2010180824
申请日：2010-08-12
申请人： Toshiba Corp , 株式会社東芝
发明人： MAEDA YUKITO
IPC分类号： G03F1/68 , G06F17/50 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To easily prepare a mask pattern accurately in a short time, the mask pattern allowing formation of a desired pattern on a substrate.SOLUTION: One embodiment of a method for preparing a mask pattern includes the following steps: In a light intensity calculation step, a corresponding relationship between the intensity of light in a peripheral region of a cell given by the cell when the cell composed of a cell pattern on a mask is subjected to a lithographic process, and a distance from an outer circumference of the cell, is calculated by using a lithography target of the cell. In an approximate pattern calculation step, a lithographic target having the same corresponding relationship as an approximate value of the above corresponding relationship is calculated as an approximate pattern. In an OPC (optical proximity correction) step, a pattern prepared by arranging the approximate pattern in a peripheral region of each cell is subjected to an OPC process. In a mask pattern preparation step, a mask pattern of each cell is prepared by extracting a cell after the OPC from the pattern subjected to the OPC process.
摘要翻译：要解决的问题：为了在短时间内容易地准确地准备掩模图案，可以在基板上形成所需图案的掩模图案。解决方案：用于制备掩模图案的方法的一个实施例包括以下步骤：在光强度计算步骤中，当单元组成时，由单元给出的单元的外围区域中的光的强度之间的对应关系进行光刻处理，并且通过使用单元的光刻对象来计算与单元的外周的距离。在近似图案计算步骤中，计算具有与上述对应关系的近似值相同的对应关系的光刻目标作为近似图案。在OPC（光学邻近校正）步骤中，通过将每个单元的周边区域中的近似图案布置而制备的图案进行OPC处理。在掩模图案准备步骤中，通过从经过OPC处理的图案中提取OPC之后的单元来制备每个单元的掩模图案。版权所有（C）2012，JPO＆INPIT

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