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1. 发明专利

JP2015056728A 発振器审中-公开
标题翻译：振荡器
公开(公告)号：JP2015056728A
公开(公告)日：2015-03-23
申请号：JP2013188372
申请日：2013-09-11
申请人：日本電波工業株式会社 , Nippon Dempa Kogyo Co Ltd
发明人： SHIOBARA TAKESHI , YODA TOMOYA
IPC分类号： H03B5/32
摘要：【課題】制御電圧入力端に印加される制御電圧に応じて、精度高く出力周波数を制御することができる発振器を提供すること。【解決手段】直流電圧である周波数調整用の制御電圧がその間に供給される制御電圧入力端及びグランド端と、前記入力端及びグランド端の間に接続され、前記制御電圧に基づいて出力周波数が調整される発振回路と、前記発振回路と前記グランド端とを接続するグランド用線路と、前記入力端と前記発振回路との間に設けられた演算増幅器を含み、前記グランド用線路の電圧降下による制御電圧の変動を抑えるための電圧安定化回路と、を備え、前記電圧安定化回路は、前記入力端と前記グランド用線路における発振回路の近傍である第1の位置との間の電圧に、前記第1の位置と前記グランド用線路におけるグランド端の近傍である第2の位置との間の電圧を加算するように構成する。【選択図】図1
摘要翻译：要解决的问题：提供可以响应于施加到控制电压输入端的控制电压来精确地控制输出频率的振荡器。解决方案：振荡器包括：控制电压输入端和控制电压输入端之间的接地端用于提供直流电压的频率调节; 连接在所述输入端和所述接地端之间的振荡电路，并输出基于所述控制电压调节的频率; 连接振荡电路和接地端的接地线; 以及电压稳定电路，其包括设置在输入端和振荡电路之间的运算放大器，并且抑制由于接地线的电压降引起的控制电压的波动。电压稳定电路被配置为将输入端与振荡电路附近的接地线上的第一位置之间的电压相加在接地端附近的接地线上的第一位置和第二位置之间的电压。

2. 发明专利

JP2007295554A Digital processing apparatus 有权
标题翻译：数字处理设备
公开(公告)号：JP2007295554A
公开(公告)日：2007-11-08
申请号：JP2007095416
申请日：2007-03-30
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： FURUHATA TSUKASA , SHIOBARA TAKESHI
IPC分类号： H03M1/08
摘要： PROBLEM TO BE SOLVED: To reduce an occurrence of spurious output caused by malfunction of an A/D converter in a digital processing apparatus after converting an analog signal having a high periodicity to a digital signal by use of the A/D converter. SOLUTION: For example, in a frequency synthesizer of a particular type of system, an A/D converter is placed on the output side of a voltage controlled oscillator and it is arranged that an output signal of the A/D converter is applied to a device which performs a digital processing, and that a result of the digital processing is D/A converted and then applied back to the voltage controlled oscillator. In this case, it is arranged that noise generated with this bandwidth noise generator is added to an input signal of the analog/digital converter. The bandwidth noise is in a bandwidth that does not affect the digital signal processing performed in the foregoing device. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了减少在数字处理装置中通过使用A / D转换器将具有高周期的模拟信号转换为数字信号之后的A / D转换器的故障引起的寄生输出的发生。解决方案：例如，在特定类型的系统的频率合成器中，A / D转换器被放置在压控振荡器的输出侧，并且将A / D转换器的输出信号设置为应用于执行数字处理的设备，并且数字处理的结果被D / A转换，然后被应用回压控振荡器。在这种情况下，将该带宽噪声发生器产生的噪声加到模拟/数字转换器的输入信号中。带宽噪声处于不影响在前述设备中执行的数字信号处理的带宽。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2013038548A Clock generation device 审中-公开
标题翻译：时钟生成装置
公开(公告)号：JP2013038548A
公开(公告)日：2013-02-21
申请号：JP2011172167
申请日：2011-08-05
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： SHIOBARA TAKESHI , ONISHI NAOKI , INAI NAOTO
IPC分类号： H03L7/183 , H03L7/14
摘要： PROBLEM TO BE SOLVED: To provide a clock generation device that generates a clock synchronous with a plurality of different reference frequencies and reduces noise generation and power consumption during a free running operation.SOLUTION: A plurality of external reference clocks can be input into the clock generation device. Signal level detection circuits 24, 25 detect band-specific levels of an input external reference signal. In response to the detected signal levels, a microcontroller 4 enables a clock selection circuit 34 to output an external reference clock via a free running control signal and selects an external reference clock at an appropriate level via a selection control signal if only one external reference signal is at an appropriate level, and if not, disables the clock selection circuit 34 from outputting an external reference clock via the free running control signal, and powers down a PLL-IC 5 and causes a voltage-controlled oscillator 9 to effect free running oscillation on the basis of a voltage from a free running control DC voltage generation circuit 6.
摘要翻译：要解决的问题：提供一种时钟发生装置，其产生与多个不同参考频率同步的时钟，并且在自由运行操作期间减少噪声产生和功耗。解决方案：可以将多个外部参考时钟输入到时钟产生装置中。信号电平检测电路24,25检测输入外部参考信号的频带特定电平。响应于检测到的信号电平，微控制器4使得时钟选择电路34经由自由运行的控制信号输出外部参考时钟，并通过选择控制信号选择适当电平的外部参考时钟，如果只有一个外部参考信号处于适当的电平，如果不是，则禁止时钟选择电路34经由自由运行控制信号输出外部参考时钟，并且使PLL-IC5断电并使压控振荡器9产生自由振荡基于来自自由运行的控制DC电压产生电路6的电压。版权所有：（C）2013，JPO和INPIT

4. 发明专利

JP2011197981A I/o extension circuit 审中-公开
标题翻译： I / O扩展电路
公开(公告)号：JP2011197981A
公开(公告)日：2011-10-06
申请号：JP2010063494
申请日：2010-03-19
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： SHIOBARA TAKESHI
IPC分类号： G06F15/78 , G06F3/00 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide an I/O extension circuit capable of expanding an I/O port, using a shift register of a versatile logic IC, and capable of enhancing an operation speed.SOLUTION: In the I/O extension circuit, a serial data, a synchronization clock and a signal of latch timing are transmitted from a one-chip microcomputer 1 to a versatile shift register IC2, using a clock synchronization system having a continuous output mode between the one-chip microcomputer 1 and the versatile shift register IC2, while the versatile shift register IC2 is constituted to cascade-connect the versatile logic IC, and the serial data is converted into a plurality of bits of parallel data, according to the received synchronization clock and the signal of the latch timing.
摘要翻译：要解决的问题：提供能够扩展I / O端口的I / O扩展电路，使用通用逻辑IC的移位寄存器，并且能够提高操作速度。解决方案：在I / O扩展电路中，串行数据，同步时钟和锁存定时信号从单片机1发送到通用移位寄存器IC2，使用在单片微机1和通用移位之间具有连续输出模式的时钟同步系统寄存器IC2，而通用移位寄存器IC2被构成为级联连接通用逻辑IC，并且串行数据根据所接收的同步时钟和锁存定时的信号被转换成多个并行数据位。

5. 发明专利

JP2010261899A Automatic inspecting system 审中-公开
标题翻译：自动检测系统
公开(公告)号：JP2010261899A
公开(公告)日：2010-11-18
申请号：JP2009114654
申请日：2009-05-11
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： SHIOBARA TAKESHI
IPC分类号： G01R31/28 , H04M3/24
摘要： PROBLEM TO BE SOLVED: To provide an automatic inspecting system that facilitates performing inspection or the like, by using a versatile interface.
SOLUTION: In the automatic inspecting system, a PC2 outputs USB commands configured such that a control command including specific identification information is for a microcomputer 13 and a control command not including specific identification information is for a synthesizing device 20. When a USB-serial conversion tool 4 converts the USB command into a serial signal so as to output it to a jig substrate 10 in a thermostatic chamber 1, the microcomputer 13 allows the synthesizing device 20 to perform operations of selecting, supplying a power and other operations for inspection on the basis of the control command including the specific identification information. The control command not including the specific identification information is output to the synthesizing device 20 via a three-state buffer 14, and data of a control result and data of an inspection result are output to the USB-serial conversion tool 4 from a negative logical sum circuit 11.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过使用多功能接口来提供便于执行检查等的自动检查系统。解决方案：在自动检测系统中，PC2输出配置为使得包括特定识别信息的控制命令用于微型计算机13的USB命令，并且不包括特定识别信息的控制命令用于合成装置20.当USB - 串行转换工具4将USB命令转换为串行信号，以便将其输出到恒温室1中的夹具基板10，微计算机13允许合成装置20执行选择，提供电源和其它操作的操作基于包括特定识别信息的控制命令进行检查。不包含特定识别信息的控制命令经由三状态缓冲器14输出到合成装置20，并且将控制结果和检查结果的数据的数据从负逻辑输出到USB串行转换工具4 总结电路11.版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2007295556A Noise reduction system of digital processor 有权
标题翻译：数字处理器噪声减少系统
公开(公告)号：JP2007295556A
公开(公告)日：2007-11-08
申请号：JP2007096914
申请日：2007-04-02
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： FURUHATA TSUKASA , SHIOBARA TAKESHI
IPC分类号： H03L7/093 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To positively and easily reduce noises of a digital processor configuring a PLL or a frequency synthesizer by using a digital signal processing circuit. SOLUTION: In the frequency synthesizer, a digital processing device 115 for executing phase comparison operation of the PLL consists of digital signal processing circuits 115A-115C. In this frequency synthesizer, a noise suppressor 115D has a circuit configuration having ON/OFF operation same as that of a digital low pass filter 115B in which a large number of logic circuit constituents almost simultaneously performs ON/OFF operation, and performs an ON/OFF operation reverse to the ON/OFF operation of the filter 115B, thereby reducing the noises. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过使用数字信号处理电路来积极和容易地减少配置PLL或频率合成器的数字处理器的噪声。解决方案：在频率合成器中，用于执行PLL的相位比较操作的数字处理装置115由数字信号处理电路115A-115C组成。在该频率合成器中，噪声抑制器115D具有与数字低通滤波器115B相同的ON / OFF操作的电路配置，其中大量的逻辑电路组成几乎同时执行ON / OFF操作，并且执行ON / OFF操作与滤波器115B的ON / OFF操作相反，从而减少噪声。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006033195A Crystal oscillator and detector 审中-公开
标题翻译：水晶振荡器和探测器
公开(公告)号：JP2006033195A
公开(公告)日：2006-02-02
申请号：JP2004206441
申请日：2004-07-13
申请人： National Institute Of Advanced Industrial & Technology , Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社 , 独立行政法人産業技術総合研究所
发明人： KOYAMA MITSUAKI , SHIOBARA TAKESHI , WAKAMATSU SHUNICHI , KUROSAWA SHIGERU , AIZAWA HIDENOBU
IPC分类号： H03B5/32 , G01N5/02 , H03H9/17 , H03H9/205
摘要： PROBLEM TO BE SOLVED: To provide a compact crystal oscillator having low power consumption and satisfactory frequency temperature characteristics. SOLUTION: First and second oscillator 1A, 1B are used as an oscillator comprising a quartz oscillator and an oscillation circuit, and for example a heterodyne detector is provided for taking out a difference in oscillation frequencies from the oscillators 1A, 1B and outputting the frequency signal of the frequency difference. A resonance frequency at the first oscillator 1A differs from that at the second one 1B, and the frequency temperature characteristics are identical with those at the second oscillator 1B. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有低功耗和令人满意的频率温度特性的紧凑型晶体振荡器。解决方案：第一和第二振荡器1A，1B用作包括石英振荡器和振荡电路的振荡器，并且例如外差检测器用于从振荡器1A，1B中取出振荡频率的差异并输出频率信号的频率差。第一振荡器1A的谐振频率与第二振荡器1A的谐振频率不同，频率温度特性与第二振荡器1B的频率温度特性相同。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2012161018A Frequency synthesizer device and manufacturing system of the same 审中-公开
标题翻译：频率合成器件及其制造系统
公开(公告)号：JP2012161018A
公开(公告)日：2012-08-23
申请号：JP2011020697
申请日：2011-02-02
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： SHIOBARA TAKESHI , KITAYAMA YASUO , ENDO TAKESHI
IPC分类号： H03L7/18
摘要： PROBLEM TO BE SOLVED: To provide a frequency synthesizer device capable of eliminating human errors in a manufacturing process or an inspection process to make proper specifications even when many, similar models are manufactured, and to provide a manufacturing system of the same.SOLUTION: The present invention relates to a frequency synthesizer device and a manufacturing system of the same. In a frequency synthesizer device 1, a hardware identifier circuit 13 stores a hardware identifier corresponding to a model, an external PC 2 stores a plurality of hardware identifiers and parameters corresponding to them. When a microcontroller 12 receives a request of the hardware identifier from the external PC 2, the microcontroller 12 reads the hardware identifier from the hardware identifier circuit 13 to output it to the external PC 2, the external PC 2 reads the parameter stored corresponding to the hardware identifier acquired from the frequency synthesizer device 1 to output it the frequency synthesizer device 1, and the microcontroller 12 stores the received parameter in a nonvolatile memory 14.
摘要翻译：解决的问题：提供即使在制造许多相似的型号时也能够消除制造过程或检查过程中的人为错误的频率合成器装置，以便制造适当的规格，并提供其制造系统。解决方案：本发明涉及一种频率合成器装置及其制造系统。在频率合成器装置1中，硬件识别电路13存储对应于模型的硬件标识符，外部PC2存储多个硬件标识符和与其对应的参数。当微控制器12从外部PC2接收到硬件标识符的请求时，微控制器12从硬件识别电路13读取硬件标识符，将其输出到外部PC2，外部PC2读取对应于从频率合成器装置1获取的硬件标识符，以将其输出到频率合成器装置1，并且微控制器12将接收的参数存储在非易失性存储器14中。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2011155599A Pll oscillator circuit 有权
标题翻译： PLL振荡器电路
公开(公告)号：JP2011155599A
公开(公告)日：2011-08-11
申请号：JP2010017075
申请日：2010-01-28
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： SHIOBARA TAKESHI
IPC分类号： H03L7/095
CPC分类号： H03L7/183 , H03L7/10
摘要： PROBLEM TO BE SOLVED: To provide a PLL oscillator circuit examining an unlock state and having an auto retry function enabling automatic resynchronization. SOLUTION: In the PLL oscillator circuit, a MPU 4 receives a lock detection signal from the PLL-IC 1 that compares an external reference signal with an output signal from a VCXO 3 in phase, and outputs a control voltage to the VCXO 3, sets data for an unlock alarm test at the PLL-IC 1 in order to turn a lock state into an unlock state when determining an unlock state with the lock detection signal from the PLL-IC 1, outputs an unlock alarm output signal to the outside, determines whether the unlock state continues for a first time period, and when the unlock state continues for the first time period, executes retry to set data for resynchronization at the PLL-IC 1. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种检测解锁状态并具有自动重试功能的PLL振荡器电路，其实现自动再同步。解决方案：在PLL振荡电路中，MPU4接收来自PLL-IC1的锁定检测信号，PLL-IC1将外部基准信号与VCXO 3的输出信号同相进行比较，并向VCXO输出控制电压如图3所示，在利用来自PLL-IC1的锁定检测信号确定解锁状态时，在PLL-IC1上设定解锁报警测试的数据，以将锁定状态转为解锁状态，将解锁报警输出信号输出到外部确定解锁状态是否持续第一时间段，并且当解锁状态持续第一时间段时，执行重试以设置PLL-IC1的再同步数据。版权所有（C）2011 ，JPO＆INPIT

10. 发明专利

JP2011040967A Pll circuit 审中-公开
标题翻译： PLL电路
公开(公告)号：JP2011040967A
公开(公告)日：2011-02-24
申请号：JP2009186066
申请日：2009-08-10
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： SHIOBARA TAKESHI , ONISHI NAOKI , KIMURA HIROKI
IPC分类号： H03L7/10 , H03L1/02 , H03L7/095 , H03L7/14
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit capable of automatically correcting aging characteristics and reducing output frequency fluctuation when an external reference signal is not connected or unlocked. SOLUTION: In the PLL circuit, when a reference signal is in a locked state within an appropriate range, upon initial adjustment, the initial voltage of a charge pump output voltage (A) is read together with temperature information T, the setting value of a DA converter or a PWM output circuit 9 is adjusted so that a voltage (B) for setting a free-running frequency becomes the voltage (A), and a temperature characteristic initial table is generated. During an operation, a setting value corresponding to the latest voltage of the voltage (A) in the temperature information T is specified by referring to the temperature characteristic initial table, the table is offset-corrected by the difference of the setting values of the initial voltage and the latest voltage to generate a temperature correction table for free running, and free running is performed by the voltage (B) for setting the free-running frequency by the specified setting value when an unlocked state or the like occurs. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种当外部参考信号未连接或解锁时能够自动校正老化特性并降低输出频率波动的PLL电路。解决方案：在PLL电路中，当参考信号处于适当范围内的锁定状态时，初始调整时，电荷泵输出电压（A）的初始电压与温度信息T一起读取，设定值调整DA转换器或PWM输出电路9的值，使得用于设定自由运行频率的电压（B）成为电压（A），并且产生温度特性初始表。在操作中，通过参照温度特性初始表来指定对应于温度信息T中的电压（A）的最新电压的设定值，该表通过初始值的设定值的差进行偏移校正电压和最新电压以产生用于自由运行的温度校正表，并且当发生解锁状态等时，通过用于将自由运行频率设定为指定设定值的电压（B）执行自由运行。版权所有（C）2011，JPO＆INPIT

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