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1. 发明专利

JP2011199339A Pll circuit 审中-公开
标题翻译： PLL电路
公开(公告)号：JP2011199339A
公开(公告)日：2011-10-06
申请号：JP2010060503
申请日：2010-03-17
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： KIMURA HIROKI
IPC分类号： H03L7/08
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit which can obtain a stable phase noise characteristic.SOLUTION: In the PLL circuit, a level detection circuit 7 detects the level of a reference frequency (Fref) signal from a reference oscillator 4, a control circuit 5 outputs to a variable ATT 6 a control signal which makes the attenuation amount of the variable ATT 6 small when the detected level is smaller than a specific value, and makes the attenuation amount of the variable ATT 6 large when the detected level is larger than the specific value, and the variable ATT 6 attenuates a reference frequency signal according to the control signal from the control circuit 5, stabilizes the input level of the reference frequency signal to a PLL IC2, and prevents a phase noise characteristic from deteriorating, so that it can prevent unlocking.
摘要翻译：要解决的问题：提供可以获得稳定的相位噪声特性的PLL电路。解决方案：在PLL电路中，电平检测电路7检测来自参考振荡器4的参考频率（Fref）信号的电平，控制电路5向变量ATT 6输出使检测电平小于特定值时变量ATT 6的衰减量小的控制信号，并且当检测到的电平较大时，变量ATT 6的衰减量较大并且变量ATT 6根据来自控制电路5的控制信号衰减参考频率信号，将参考频率信号的输入电平稳定在PLL IC2中，并且防止相位噪声特性恶化，因此它可以防止解锁。

2. 发明专利

JP2007228568A Vco drive circuit and frequency synthesizer 有权
标题翻译： VCO驱动电路和频率合成器
公开(公告)号：JP2007228568A
公开(公告)日：2007-09-06
申请号：JP2007015923
申请日：2007-01-26
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： KITAYAMA YASUO , KIMURA HIROKI , ONISHI NAOKI , TSUKAMOTO NOBUO
IPC分类号： H03L7/093 , H03L7/107 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To provide a VCO drive circuit that reduces impedance at the control terminal side of a VCO, prevents phase noise characteristics from being deteriorated in the VCO, and maintains a natural frequency at a fixed value to the solid variation of the VCO and temperature change, and to provide a frequency synthesizer. SOLUTION: In the VCO drive circuit, there are provided: a DAC4 for coarse control for D/A-converting the digital data of a frequency for coarse control; a DAC6 for fine control for D/A-converting the digital data of a frequency for fine control; an LPF5 that removes the noise of output from the DAC4 for coarse control as input to the control terminal of the VCO and has slow response speed; and an LPF7 that converts output from the DAC6 for fine control to voltage and has fast response speed for smoothing a signal; and a resistor R6 for connecting the input stage of the LPF 5 to that of the LPF 7; a capacitor C8 for capacitively coupling the output of the LPF 5 to that of the LPF 7; and a variable resistor R4 as a voltage control means in the LPF 7. The frequency synthesizer has the VCO drive circuit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供降低VCO的控制端侧的阻抗的VCO驱动电路，防止VCO中的相位噪声特性劣化，并将固有频率保持在固定值的固定值的VCO和温度变化，并提供频率合成器。解决方案：在VCO驱动电路中，提供：用于粗调控制的DAC4，用于对用于粗略控制的频率的数字数据进行D / A转换; 一个DAC6，用于精细控制，用于对数字数据进行D / A转换，以进行精细控制; 一个LPF5，将去除DAC4输出的噪声作为对VCO控制端子的输入进行粗略控制，响应速度慢; 以及将DAC6的输出转换为电压，并具有快速响应速度以平滑信号的LPF7; 以及用于将LPF 5的输入级与LPF 7的输入级连接的电阻器R6; 用于将LPF 5的输出电容耦合到LPF 7的输出的电容器C8; 以及作为LPF7中的电压控制装置的可变电阻器R4。频率合成器具有VCO驱动电路。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2015053577A 発振器及び発振器の製造方法有权
标题翻译：振荡器和制造振荡器的方法
公开(公告)号：JP2015053577A
公开(公告)日：2015-03-19
申请号：JP2013184829
申请日：2013-09-06
申请人：日本電波工業株式会社 , Nippon Dempa Kogyo Co Ltd
发明人： KIMURA HIROKI
IPC分类号： H03B19/14
摘要：【課題】サブバンド信号のスプリアス特性を改善する。【解決手段】発振信号を生成する発振部10と、発振信号に基づいて、それぞれ周波数が異なる複数のサブバンド信号を生成する複数のサブバンド信号生成部20と、複数のサブバンド信号から選択されたサブバンド信号を出力する出力部30と、出力部30が出力するサブバンド信号を選択するとともに、当該選択の結果に基づいて、複数のサブバンド信号生成部20が有する複数の回路の動作モードを制御する制御部40と、を備える。【選択図】図1
摘要翻译：要解决的问题：提高子带信号的杂散特性。解决方案：振荡器包括：振荡部分10，用于产生振荡信号; 多个子带信号生成部分20，用于分别基于振荡信号产生具有不同频率的多个子带信号; 输出部分30，用于输出从多个子带信号中选出的一个; 以及控制部分40，用于选择从输出部分30输出的子带信号，并且基于选择结果控制多个子带信号产生部分20的多个电路的操作模式。

4. 发明专利

JP2014192578A Oscillation device 有权
标题翻译：振荡器件
公开(公告)号：JP2014192578A
公开(公告)日：2014-10-06
申请号：JP2013064280
申请日：2013-03-26
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： KIMURA HIROKI , DEMURA HIROYUKI , ONISHI NAOKI
IPC分类号： H03L7/095 , H03B5/32 , H03L1/02 , H03L7/14
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of notifying the exterior of a time point when an oscillation frequency of an oscillation device after power-on is stabilized, with high accuracy, in an oscillation device including an oscillator with a constant-temperature bath.SOLUTION: A device is configured to have: a heater for maintaining a temperature of an atmosphere in which a piezoelectric vibrator configuring an oscillation circuit is provided to a setting temperature; a temperature sensor detecting the temperature of the atmosphere and outputting a corresponding signal; a control circuit notifying the exterior of that an oscillation frequency outputted from the oscillation circuit is stabilized after receiving from the temperature sensor a first detection signal indicating that the temperature of the atmosphere becomes the setting temperature by the heater, after power-on; and a storage part storing correspondence between a second detection signal outputted from the temperature sensor to the control circuit at power-on, and a delay time from when the control circuit receives the first detection signal to when the notification is performed.
摘要翻译：要解决的问题：提供一种能够在上电稳定后稳定振荡装置的振荡频率的时间点通知外部的技术，在具有恒温槽的振荡器的振荡装置中，解决方案：一种装置被配置为具有：将构成振荡电路的压电振动器的气氛的温度保持在设定温度的加热器; 检测大气温度并输出相应信号的温度传感器; 通过外部通知外部振荡电路输出的振荡频率的控制电路在电源接通之后，从温度传感器接收到表示大气温度成为设定温度的第一检测信号，使其稳定; 以及存储部，其将上述从上述温度传感器输出的上述第二检测信号与上述控制电路的对应关系以及从上述控制电路接收上述第一检测信号到上述通知的延迟时间。

5. 发明专利

JP2011188305A Pll apparatus 有权
标题翻译： PLL装置
公开(公告)号：JP2011188305A
公开(公告)日：2011-09-22
申请号：JP2010052250
申请日：2010-03-09
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： KIMURA HIROKI
IPC分类号： H03L7/095 , H03L7/083 , H03L7/093
CPC分类号： H03L7/14 , H03L1/02
摘要： PROBLEM TO BE SOLVED: To prevent operation from being made to be unstable by temperature, in a PLL (phase locked loop) apparatus which specifies whether an amplitude level of a reference frequency signal from the outside is settled within a proper range, and supplies a control voltage to a voltage controlled oscillator in accordance with whether the amplitude level is inside or outside of the proper range. SOLUTION: A PLL apparatus is configured to include: a switching unit for switching a signal to be supplied to a control voltage output unit between a phase comparison unit and an auxiliary signal supplying unit; a protecting circuit which is provided between a signal path for a reference frequency signal and a ground and to which a diode is connected in inverse parallel in order to regulate an amplitude level of the reference frequency signal; a temperature detecting unit for detecting an atmospheric temperature of the protecting circuit; and a level detecting unit for detecting the amplitude level of the reference frequency signal from the outside. A threshold to be a reference of switching is set in accordance with the detected temperature, thereby dealing with a change in amplitude level caused by temperature characteristics of the diode is performed. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题为了防止由于温度而使操作不稳定，在指定来自外部的参考频率信号的振幅电平是否在适当范围内的PLL（锁相环）装置中，并且根据振幅水平是否在适当范围内或之外，向压控振荡器提供控制电压。解决方案：PLL装置被配置为包括：切换单元，用于切换要提供给相位比较单元和辅助信号提供单元之间的控制电压输出单元的信号; 保护电路设置在用于参考频率信号的信号路径和地之间，二极管并联连接到其上以便调节参考频率信号的幅度电平; 温度检测单元，用于检测保护电路的大气温度; 以及电平检测单元，用于从外部检测参考频率信号的幅度电平。根据检测到的温度设定作为开关基准的阈值，由此执行由二极管的温度特性引起的振幅电平的变化。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2011040967A Pll circuit 审中-公开
标题翻译： PLL电路
公开(公告)号：JP2011040967A
公开(公告)日：2011-02-24
申请号：JP2009186066
申请日：2009-08-10
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： SHIOBARA TAKESHI , ONISHI NAOKI , KIMURA HIROKI
IPC分类号： H03L7/10 , H03L1/02 , H03L7/095 , H03L7/14
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit capable of automatically correcting aging characteristics and reducing output frequency fluctuation when an external reference signal is not connected or unlocked. SOLUTION: In the PLL circuit, when a reference signal is in a locked state within an appropriate range, upon initial adjustment, the initial voltage of a charge pump output voltage (A) is read together with temperature information T, the setting value of a DA converter or a PWM output circuit 9 is adjusted so that a voltage (B) for setting a free-running frequency becomes the voltage (A), and a temperature characteristic initial table is generated. During an operation, a setting value corresponding to the latest voltage of the voltage (A) in the temperature information T is specified by referring to the temperature characteristic initial table, the table is offset-corrected by the difference of the setting values of the initial voltage and the latest voltage to generate a temperature correction table for free running, and free running is performed by the voltage (B) for setting the free-running frequency by the specified setting value when an unlocked state or the like occurs. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种当外部参考信号未连接或解锁时能够自动校正老化特性并降低输出频率波动的PLL电路。解决方案：在PLL电路中，当参考信号处于适当范围内的锁定状态时，初始调整时，电荷泵输出电压（A）的初始电压与温度信息T一起读取，设定值调整DA转换器或PWM输出电路9的值，使得用于设定自由运行频率的电压（B）成为电压（A），并且产生温度特性初始表。在操作中，通过参照温度特性初始表来指定对应于温度信息T中的电压（A）的最新电压的设定值，该表通过初始值的设定值的差进行偏移校正电压和最新电压以产生用于自由运行的温度校正表，并且当发生解锁状态等时，通过用于将自由运行频率设定为指定设定值的电压（B）执行自由运行。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2007267375A Oscillator and frequency synthesizer 有权
标题翻译：振荡器和频率合成器
公开(公告)号：JP2007267375A
公开(公告)日：2007-10-11
申请号：JP2007043790
申请日：2007-02-23
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： ONISHI NAOKI , KITAYAMA YASUO , KIMURA HIROKI
IPC分类号： H03L7/187 , H03L7/093
摘要： PROBLEM TO BE SOLVED: To provide an oscillator and frequency synthesizer in which deterioration in phase noise characteristics of a VCO is prevented by reducing impedance watched from a control terminal of the VCO, and generation of spurious can be prevented by reducing noise to be applied to the VCO. SOLUTION: The present invention relates to the oscillator including: a VCO 9; a control circuit 3 which outputs digital data of a frequency for rough control and digital data of a frequency for precise control; a DAC 4 for rough control which outputs the digital data of the frequency for rough control in the form of an analog signal; a DAC 6 for precise control which outputs the digital data of the frequency for precise control in the form of an analog signal; an LPF 5 of low response speed which eliminates noise in an output from the DAC 4 for rough control and inputs it to a control terminal of the VCO 9; an LPF 7 of high response speed which converts an output from the DAC 6 for precise control into a voltage and performs smoothing of a control voltage; and a synthesizer 8 which composes signals from both the LPFs 5, 7, wherein the VCO 9, the LPF 5, the LPF 7, and the synthesizer 8 are housed in a shield case. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种振荡器和频率合成器，其中通过降低从VCO的控制端观察到的阻抗来防止VCO的相位噪声特性的劣化，并且可以通过将噪声降低到应用于VCO。振荡器本发明涉及振荡器，包括：VCO 9; 输出用于粗略控制的频率的数字数据和用于精确控制的频率的数字数据的控制电路3; 用于粗略控制的DAC4，其以模拟信号的形式输出用于粗略控制的频率的数字数据; 用于精确控制的DAC6，其以模拟信号的形式输出用于精确控制的频率的数字数据; 低响应速度的LPF 5，消除了DAC4的输出中的粗略控制的噪声，并将其输入到VCO 9的控制端; 一个高响应速度的LPF 7，它将来自DAC6的输出转换成精确的控制，并进行控制电压的平滑化; 以及组合来自两个LPF 5,7的信号的合成器8，其中VCO 9，LPF 5，LPF 7和合成器8容纳在屏蔽壳中。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007259431A Pll circuit 有权
标题翻译： PLL电路
公开(公告)号：JP2007259431A
公开(公告)日：2007-10-04
申请号：JP2007043789
申请日：2007-02-23
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： KIMURA HIROKI , FURUHATA TSUKASA , KITAYAMA YASUO , ONISHI NAOKI
IPC分类号： H03L7/093
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit which can absorb vibration of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band. SOLUTION: The PLL circuit comprises, at the succeeding stage of a phase comparator, a first register 6 for storing a first parameter for controlling the loop gain, a first multiplier 7 for multiplying the output of the phase comparator 4 by a first parameter, a second register 12 for storing a second parameter for controlling the response characteristic, a second multiplier 13 for multiplying the output of the first multiplier by a second parameter, and a CPU 20 for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以吸收由于温度和个体差异引起的相位噪声特性的振荡的PLL电路，并且具有在宽频带中稳定的相位噪声抑制特性。解决方案：PLL电路在相位比较器的后级包括用于存储用于控制环路增益的第一参数的第一寄存器6，用于将相位比较器4的输出乘以第一乘法器的第一乘法器7 参数，用于存储用于控制响应特性的第二参数的第二寄存器12，用于将第一乘法器的输出乘以第二参数的第二乘法器13和用于根据第一寄存器的第一和第二寄存器设置最佳参数的CPU 20 使用频段，环境温度和设备个体差异。通过将环路增益和响应特性控制为最佳值，实现了宽频带中良好的抑制特性。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2013055521A Frequency synthesizer 审中-公开
标题翻译：频率合成器
公开(公告)号：JP2013055521A
公开(公告)日：2013-03-21
申请号：JP2011192617
申请日：2011-09-05
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： KIMURA HIROKI , SHIOBARA TAKESHI
IPC分类号： H03L7/10 , H03L7/14 , H03L7/22
摘要： PROBLEM TO BE SOLVED: To provide a frequency synthesizer that can minimize a variation in an output frequency in the event of an input interruption of an external reference signal by implementing high speed switching to output a constant voltage as a control voltage to an oscillator.SOLUTION: In the frequency synthesizer, a control circuit 11 receives a detection output from a detection circuit 10, outputs to a SW 3 a switching signal to output an output of a PLL-IC 1 to a loop filter 4 when an external reference input signal is "on," and outputs to the SW 3 a switching signal to output an output of a variable resistance 2 to the loop filter 4 if the external reference input signal is "off," and a high speed switching circuit 12 outputs to the SW 3 a switching signal to output the output of the variable resistance 2 to the loop filter 4 earlier than the control circuit 11 when detecting that the external reference input signal is "off."
摘要翻译：要解决的问题：提供一种频率合成器，其可以通过实施高速切换以将作为控制电压的恒定电压输出到外部参考信号的输入中断的输出频率的变化来最小化振荡器解决方案：在频率合成器中，控制电路11接收来自检测电路10的检测输出，向SW 3输出切换信号，以在外部的时候将PLL-IC1的输出输出到环路滤波器4 参考输入信号为“on”，如果外部基准输入信号为“off”，则向SW3输出切换信号，将可变电阻2的输出输出到环路滤波器4，高速切换电路12输出在检测到外部参考输入信号为“关闭”时，向SW 3提供切换信号，以便在控制电路11之前将可变电阻2的输出输出到环路滤波器4。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2011172071A Pll circuit 有权
标题翻译： PLL电路
公开(公告)号：JP2011172071A
公开(公告)日：2011-09-01
申请号：JP2010034758
申请日：2010-02-19
申请人： Nippon Dempa Kogyo Co Ltd , 日本電波工業株式会社
发明人： KIMURA HIROKI , ONISHI NAOKI , TSUCHIYA SHOICHI
IPC分类号： H03L7/08 , H03L7/18
CPC分类号： H03L7/08 , G06F1/0328
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit which can reduce power consumption and improve reliability without deteriorating noise characteristics. SOLUTION: The PLL circuit is provided with a PLL IC 2 which divides an output frequency Fout from a VCO 1, compares its phase with a reference signal and feeds a phase difference back to the VCO 1 as a control voltage. A control circuit 6 can finely set both a reference frequency Fref and an output frequency Fdds of a DDS circuit 5. By the combination of them, a loopback signal of the Fdds with respect to the Fref and its multiplied frequency is generated by the DDS circuit 5 and amplified by a first AMP 7, and then a desired Fdds (desired) is selected by a variable filter 8 and amplified by a second AMP 9 for supply to the PLL IC 2 as a reference signal. The control circuit 6 also supplies the PLL IC 2 with a frequency division ratio N. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以在不降低噪声特性的情况下降低功耗并提高可靠性的PLL电路。解决方案：PLL电路配备有将IC1的输出频率Fout分频的PLL IC2，将其相位与参考信号进行比较，并将相位差反馈给VCO1作为控制电压。控制电路6可以精细地设定DDS电路5的参考频率Fref和输出频率Fdds。通过它们的组合，相对于Fref及其相乘频率的Fdds的环回信号由DDS电路产生 5并由第一AMP 7放大，然后通过可变滤波器8选择所需的Fdd（期望），并由第二AMP 9放大，以供给PLL IC2作为参考信号。控制电路6还为PLL IC2提供分频比N.版权所有（C）2011，JPO＆INPIT

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