专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2009284042A Pulse detection device, and pulse detection method 审中-公开
标题翻译：脉冲检测装置和脉冲检测方法
公开(公告)号：JP2009284042A
公开(公告)日：2009-12-03
申请号：JP2008131543
申请日：2008-05-20
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： KASHIWAGI YOSHIKI
IPC分类号： H03K5/19 , H03K5/153
CPC分类号： H03K5/1252
摘要： PROBLEM TO BE SOLVED: To highly accurately detect a pulse signal.
SOLUTION: A pulse detection device 1 detects a pulse signal including an intermediate potential during a predetermined period. The pulse detection device 1 is provided with a signal fixing means for fixing the intermediate potential of the pulse signal at a low level or a high level. The signal fixing means is preferably a pull-down resistor 9 or a pull-up resistor which is connected to an input signal line to which the pulse signal is input. A pulse detection method includes a signal fixing step of fixing the intermediate potential of the pulse signal at the low level or the high level.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：高精度地检测脉冲信号。解决方案：脉冲检测装置1在预定时段内检测包括中间电位的脉冲信号。脉冲检测装置1设置有用于将脉冲信号的中间电位固定在低电平或高电平的信号固定装置。信号固定装置优选地是连接到输入脉冲信号的输入信号线的下拉电阻器9或上拉电阻器。脉冲检测方法包括将脉冲信号的中间电位固定在低电平或高电平的信号固定步骤。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2005242697A Method for verifying delay time 审中-公开
标题翻译：验证延迟时间的方法
公开(公告)号：JP2005242697A
公开(公告)日：2005-09-08
申请号：JP2004052048
申请日：2004-02-26
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI , KASHIWAGI YOSHIKI
IPC分类号： G06F17/50 , H01L21/82 , H04L12/26
CPC分类号： G06F17/5022
摘要： PROBLEM TO BE SOLVED: To provide a delay time verification method capable of verifying whether delay time in a section to be verified satisfies prescribed timing restriction or not even when the reverse phenomenon of a temperature characteristic appears.
SOLUTION: The delay time of the verification section is calculated by using a delay time MIN table 11 prepared at the minimum temperature in an operation guarantee range at first (step S11). Then the delay time of the verification section is calculated by using a delay time MIN table 12 prepared at the maximum temperature in the operation guarantee range (step S12). Then whether the delay time of the verification section satisfies the prescribed timing restriction or not is verified by using the shorter delay time out of the delay time calculated in the step S11 and the delay time calculated in the step S12 (step S13).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种延迟时间验证方法，即使当出现温度特性的反向现象时，能够验证待验证的部分中的延迟时间是否满足规定的时序限制。解决方案：首先通过使用在最低温度下制备的延迟时间MIN表11来计算验证部分的延迟时间（步骤S11）。然后，通过使用在操作保证范围内的最高温度下准备的延迟时间MIN表12来计算验证部的延迟时间（步骤S12）。然后，通过使用在步骤S11中计算的延迟时间中的较短的延迟时间和在步骤S12中计算的延迟时间来验证验证部分的延迟时间是否满足规定的时序限制。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004335843A Semiconductor circuit device designing method, designed semiconductor circuit device, designing system, and recording medium 有权
公开(公告)号：JP2004335843A
公开(公告)日：2004-11-25
申请号：JP2003131472
申请日：2003-05-09
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： KASHIWAGI YOSHIKI , KATO TETSUYA
IPC分类号： G06F9/45 , G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/00
CPC分类号： G06F17/5045
摘要： PROBLEM TO BE SOLVED: To provide a highly efficient semiconductor circuit device designing technique. SOLUTION: For designing a chip having a plurality of circuits that operate on different power sources, boundary cells are prepared in advance to be inserted into the boundary regions between the circuits. By using a designing tool, the boundary cells are inserted into the boundary regions after a logic circuit level net list is generated. The boundary cells are connected to signal transmission lines between the circuits, and are utilized for controlling penetration currents and leak currents. Chip designing is facilitated when such boundary cells are stored ready for use in a cell library. COPYRIGHT: (C)2005,JPO&NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式