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1. 发明专利

JPH03120862A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03120862A
公开(公告)日：1991-05-23
申请号：JP26040489
申请日：1989-10-04
申请人： NEC CORP
发明人： AOMURA KUNIO
IPC分类号： H01L27/10 , G11C11/405
摘要： PURPOSE:To widen the base width of a bipolar transistor, which uses a first diffused region as its base region, to reduce a current amplification factor and to make it possible to realize a memory cell semiconductor device, which is actuated with a low current and high in reliability and efficiency, by a method wherein the depth of the P-N junction of the first diffused region is made deeper than that of the P-N junction of a second diffused region. CONSTITUTION:A semiconductor device is formed into one having an inverse conductivity type region 3 provided on a one conductivity type semiconductor substrate (a P-type silicon substrate) 1, a field insulating film (a field oxide film) 4, which is provided on the surface of the region 3 and partitions an element formation region, a gate electrode 5 provided on the element formation region through a gate insulating film, a one conductivity type first diffused region 12, which is provide in the element formation region and aligned to the electrode 5 and has a deep P-N junction, a one conductivity type second diffused region (a P-type diffused region) 9 having a P-N junction shallower than that of the region 12 and an inverse conductivity type third diffused region 11 provided in the aboove region 12. For example, a MOS transistor and a bipolar transistor, which uses an N buried region 2 and an N region 3 as its collector region, uses a P-type diffused region 12 as its base region and uses an N diffused region 11 as its emitter region, are constituted.

2. 发明专利

JPS6393143A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6393143A
公开(公告)日：1988-04-23
申请号：JP23972086
申请日：1986-10-07
申请人： NEC CORP
发明人： AOMURA KUNIO , HAMANO KUNIYUKI
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8249 , H01L27/07 , H01L29/73 , H01L29/78
摘要： PURPOSE:To constitute a semiconductor device of a structure, wherein a bipolar transistor and a MOS transistor are mixed, by a method wherein an N-type region is provided in the P-type drain of a P-MOS transistor Tr, and the P-MOS Tr and an N-P-N Tr are integrally constituted. CONSTITUTION:The N-type well region of a P-MOS Tr and an N-type region 13 to become to the collector region of an N-P-N Tr are formed in a P-type substrate 11 and an electrode leading-out region 19 is provided in this region 13. Moreover, P-type source and drain regions 16 and 17 are provided on both sides of the gate electrode 15 of the P-MOS Tr and a high-concentration N-type region 18 is selectively provided in this drain region. thereby, the N-P-N Tr is formed using the drain region 17 as its base, using the N-type region 18 provided in the drain region as its emitter and moreover, using the N-type region 13 in the P-type substrate 11 as its collector.

3. 发明专利

JPS618940A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS618940A
公开(公告)日：1986-01-16
申请号：JP13045684
申请日：1984-06-25
申请人： Nec Corp
发明人： AOMURA KUNIO
IPC分类号： H01L27/06 , H01L21/762
CPC分类号： H01L21/76297
摘要： PURPOSE:To contrive uniformity of characteristics of elements by forming the second semiconductor layer on a back surface of the semiconductor substrate which is made thin by removing the back surface after forming grooves on a surface of a semiconductor substrate and covering the substrate with an insulating film. CONSTITUTION:After a front surface of an N Si substrate 21 is etched to form a groove 22, the first oxide film 23 is formed and then a polysilicon layer 24 is formed to fill said groove 22. Next, a back surface of the N Si layer 21 is ground away gradually and the first oxide film 23 which is formed at the bottom of the groove 22 is exposed to form an island-shaped N layer 21'. On the ground plane of N layer 21, an N type Si layer 25 is formed and then the thin second oxide film 26 and a nitride film 27 are formed on said layer 25, after which apertures 28 are arranged on them. Subsequently, the N type Si layer 25 is oxidized by thermal oxidation and the third oxide film 29 for element isolation whose lower end is in contact with the first oxide film 23 which is formed at the bottom of the groove 22 is formed. Consequently, the N type Si layer 25 becomes an island-shaped N type element forming region 25' thereby facilitating the control of a thickness of said region 25'.
摘要翻译：目的：通过在半导体衬底的表面上形成凹槽之后通过去除背面而在半导体衬底的背面上形成第二半导体层来形成元件的特性的均匀性，并用绝缘膜覆盖衬底。构成：在蚀刻N + Si基板21的前表面以形成凹槽22之后，形成第一氧化膜23，然后形成多晶硅层24以填充所述凹槽22.接下来，将N + Si层21逐渐磨去，形成在槽22的底部的第一氧化物膜23暴露形成岛状N +层21'。在N +层21的接地面上，形成N型Si层25，然后在所述层25上形成薄的第二氧化膜26和氮化物膜27，然后在其上配置有孔28。随后，通过热氧化来氧化N型Si层25，并且形成下端与形成在槽22的底部的第一氧化物膜23接触的用于元件隔离的第三氧化膜29。因此，N型Si层25成为岛状N型元件形成区域25'，从而有助于控制所述区域25'的厚度。

4. 发明专利

JPH03278572A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03278572A
公开(公告)日：1991-12-10
申请号：JP7921290
申请日：1990-03-28
申请人： NEC CORP
发明人： AOMURA KUNIO
IPC分类号： H01L27/108 , H01L21/8242
摘要： PURPOSE:To obtain an easy-to-use device and to reduce power by setting the concentration of impurity in a first region having a third region lower than the concentration of impurity in a second region thereby employing only one supply voltage for a memory device. CONSTITUTION:A burried N-type high concentration region 2 and a low concentration N-type region 3 are provided on a P-type silicon substrate 1, where P-type first and second regions 12, 9 are provided in the N-type region thus constituting a MOS transistor having the first and second regions 12, 9 as a source region or a drain region. On the other hand, an N-type high concentration third region 11 is provided in the first region 12 thus constituting a bipolar transistor having the N-type regions 2, 3 as collector regions, the first region 12 as base region and the third region 11 as emitter region. Impurity concentration in the first region is set lower than that in the second region.

5. 发明专利

JPS62134941A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62134941A
公开(公告)日：1987-06-18
申请号：JP27541385
申请日：1985-12-06
申请人： NEC CORP
发明人： AOMURA KUNIO
IPC分类号： H01L21/76
摘要： PURPOSE:To effectively and significantly reduce the size of an integrated circuit device and to enhance the density of the circuit device by ohmically contacting a polycrystalline silicon at least at part of sidewall face of an insular portion with at least first impurity layer of the insular portion to be electrically connected. CONSTITUTION:A high density N-type impurity is selectively added to a polycrystalline silicon region formed by filling a polycrystalline silicon in a groove through an insulating oxide film 15 and heat treated in the state that the part of the sidewall of an insular portion and the bottom of the groove on the inner surface of a substrate 11 are exposed to form an N-type high density polycrystalline silicon region 16. Since the region 16 has an N-type high density, the region 16 at least at part of the sidewall is ohmically contacted with both at least first and second impurity layers 12, 13 in the insular portion to be electrically connected. Since the film 15 is disposed at the side wall face separated from the sidewall of the insular portion, the layers 12, 13 and the region 16 on the sidewall are effectively electrically separated by the insulating oxide 15.

6. 发明专利

JPS61168952A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61168952A
公开(公告)日：1986-07-30
申请号：JP943785
申请日：1985-01-22
申请人： NEC CORP
发明人： AOMURA KUNIO
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To improve accuracy of a resistor, by constituting the impurities in the region at the corner of the resistor having a bent flat structure having the corner by high-concentration impurities, in comparison with the surrounding area of said region. CONSTITUTION:A resistor has a flat structure, which is bent in and L shape. The resistance value R1 of this resistor is basically the series resistances of two rectangle parts and a corner part. The resistance value of the corner part is sufficiently low with respect to the total resistance value R1 when the impurity concentration of the corner part 15 is made higher than that of other parts 12a and 12b. Since the resistance values of the rectangle parts 12a and 12b can be accurately designed, the accuracy of R1 can be enhanced.

7. 发明专利

JPS59204251A Semiconduttor device of small wiring capacitance 失效
标题翻译：小型接线电容的半导体器件
公开(公告)号：JPS59204251A
公开(公告)日：1984-11-19
申请号：JP7897583
申请日：1983-05-06
申请人： Nec Corp
发明人： AOMURA KUNIO
IPC分类号： H01L21/76 , H01L21/763 , H01L21/768 , H01L23/522
CPC分类号： H01L21/763
摘要： PURPOSE:To reduce the decrease of speed by a method wherein the wiring capacitance is reduced by making the surface of a semiconductor substrate of the part other than the circuit element region and the isolation region deeper than the surface of the semiconductor substrate at the circuit element region and shallower than that of said substrate at the isolation region. CONSTITUTION:Isulation film thicknesses under wirings 38, 38', 38'' are different with rigions. The position of the surface of the Si substrate is at the position A at the circuit element region, C at the isolation region, and B at the other region. Thereby, the wiring capacitance between the wiring and the Si substrate per unit area is small at the isolation region, large at the circuit element region, and the medium value thereof at the ther region. Therefore, the wiring capacitance becomes smaller than conventioanl, resulting in the reduction of the decrease of speed.
摘要翻译：目的：为了减少速度的降低，其中通过使电路元件区域以外的部分的半导体衬底的表面和隔离区域比电路元件处的半导体衬底的表面更深而减小布线电容并且在隔离区域比所述衬底浅。构成：配线38,38'，38“的配线膜厚度与配件不同。 Si衬底的表面的位置在电路元件区域处的位置A处于隔离区域处的C，而在另一区域处的B。由此，布线与单位面积的Si衬底之间的布线电容在隔离区域较小，在电路元件区域较大，在其它区域的介质值较小。因此，布线电容变得小于conventioanl，导致速度降低的降低。

8. 发明专利

JPS5735370A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5735370A
公开(公告)日：1982-02-25
申请号：JP11060180
申请日：1980-08-12
申请人： Nec Corp
发明人： AOMURA KUNIO
IPC分类号： H01L29/43 , H01L21/28 , H01L21/331 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To reduce the base resistance by connecting a metal silicide layer provided on the surface of an inactive base region to an external eletrode through a hole part in an insulting film. CONSTITUTION:The device is constituted by an N type collector region 11, a P type ba region 12, an N type emitter region 13, and external electrode 17 and 17' in said regions. A platinum silicide layer 15 is provided on the surface of the base region 12, and the resistance from the external electrode 17 for the base on the hole provided in the insulating film 16 to the emitter region 13 is decreased.
摘要翻译：目的：通过将设置在非活性基底区域的金属硅化物层与绝缘膜上的孔部分的外部电极连接来降低基极电阻。构成：该装置由所述区域中的N型集电极区域11，P型区域12，N型发射极区域13和外部电极17和17'构成。在基极区域12的表面上设置有铂硅化物层15，并且从设置在绝缘膜16上的孔的基极的外部电极17的电阻降低到发射极区域13。

9. 发明专利

JPH0290617A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0290617A
公开(公告)日：1990-03-30
申请号：JP24500188
申请日：1988-09-28
申请人： NEC CORP
发明人： AOMURA KUNIO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762
摘要： PURPOSE:To improve the reproducibility, the yield and the reliability of the title semiconductor device by a method wherein, after a first groove has been formed in the semiconductor device, a first insulator is buried, an aperture is formed in the prescribed region after a mask layer has been formed on the whole surface, and a second insulator is buried after a second groove has been formed using the mask layer and the first insulator as a mask. CONSTITUTION:An N type layer 2 and an N type epitaxial layer 3 are formed on a P-type silicon substrate 1, the substrate is selectively etched using a mask layer 4 as a mask, and the mask layer 4 is removed after a first groove 5A, which reaches the P-type silicon substrate 1, has been formed. P-type impurities are introduced to the bottom part of the first groove 5A, a P type region 7 is formed, and a first layer 6A is buried in the first groove 5A. Then, a mask layer 4 is formed again on the surface of the substrate, an aperture 8A is selectively formed, the substrate is selectively etched using a mask layer 4A and the first insulator 6A as masks, and after a second groove 5B of the second groove 5B has been formed in such a manner that its bottom reaches the N type epitaxial layer 3 or the part located close to the surface of the N+ type layer 2, the mask layer 4A is removed, and the second insulator 6B is buried in the second groove 5B.

10. 发明专利

JPS6427266A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6427266A
公开(公告)日：1989-01-30
申请号：JP18391187
申请日：1987-07-22
申请人： NEC CORP
发明人： AOMURA KUNIO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/72 , H01L29/732
摘要： PURPOSE:To inhibit base resistance at a low value while obtaining high breakdown strength by determining the position of an emitter forming opening section while forming the end section of a high-concentration base region on the emitter region side by a mask for shaping the emitter and a mask including a polycrystalline silicon layer formed onto the sidewall of the mask. CONSTITUTION:A polycrystalline silicon layer 5 is deposited onto the surface containing an silicon nitride film 3, and the polycrystalline silicon layer 5 and the silicon nitride film 3 are etched selectively in succession, thus shaping a mask for forming an emitter. A polycrystalline silicon layer 6 is deposited onto the surface including the mask, and the polycrystalline silicon layer 6 is left only on the sidewall of the mask through the anisotropic etching of the whole surface, and others are removed. Boron ions are implanted in high concentration through a self-alignment manner, P type base regions 7 are shaped into base forming regions, the polycrystalline silicon layers 5, 6 are removed, and boron ions are implanted in low concentration and an P type base region 8 connected to the P type base regions 7 is formed. Accordingly, junction breakdown strength is increased under the state in which base resistance is inhibited at a low value, thus reducing leakage currents.

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