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1. 发明专利

JPWO2016038709A1 半導体集積回路装置および半導体集積回路装置の製造方法审中-公开
公开(公告)号：JPWO2016038709A1
公开(公告)日：2017-06-29
申请号：JP2016547310
申请日：2014-09-11
申请人：ルネサスエレクトロニクス株式会社
发明人：直剛渡辺 , 直剛渡辺
IPC分类号： G01R31/28 , G01R31/26 , G01R31/30 , H01L21/822 , H01L27/04
CPC分类号： H01L23/5256 , G01R31/28 , H01L21/70 , H01L21/82 , H01L23/5383 , H01L27/11 , H01L29/72 , H01L2924/0002
摘要：半導体集積回路装置1000は、第1回路を有する第1半導体チップCHP1と、第2回路を有し、第1半導体チップとは異なる第2半導体チップCHP2とを具備する。半導体集積回路装置1000は、バーイン試験のとき、制御信号に従って、第1回路および第2回路の動作を制御する制御回路BTCNTを具備し、バーイン試験のとき、第1回路が動作することにより第1半導体チップCHP1に作用するストレス量と、第2回路が動作することにより第2半導体チップCHP2に作用するストレス量とが異なるように、制御回路BTCNTは第1回路および第2回路を制御する。

2. 发明专利

JPWO2016042592A1 センサ装置有权
公开(公告)号：JPWO2016042592A1
公开(公告)日：2017-04-27
申请号：JP2016548456
申请日：2014-09-16
申请人：日立オートモティブシステムズ株式会社
发明人：松本　昌大 , 昌大松本 , 中野　洋 , 洋中野 , 善光柳川 , 善光柳川 , 晃小田部 , 晃小田部
IPC分类号： G01D21/00 , G01D3/032
CPC分类号： H01L27/0255 , G01D21/00 , H01L21/822 , H01L23/552 , H01L27/0288 , H01L27/04 , H01L29/72 , H01L29/861
摘要：従来のセンサ装置では自動車用センサ装置の出力端子に要求されるEMC耐性とESD耐性を両立すること困難であった。本実施例のセンサ装置1は本実施例のセンサ装置1は電源を供給する電源端子2と接地端子3と、物理量に応じて電気的特性の変化するセンサ素子4と、センサ素子4からの出力信号を処理する信号処理集積回路I4と、信号処理集積回路I4で処理された出力信号を出力する出力端子とから構成される。また、信号処理集積回路I4はセンサ素子4からの出力信号を処理する信号処理回路I4と、出力端子4と信号処理回路14の間に接続され、絶縁膜上に配置された抵抗素子6と、出力端子16と接地端子4の間に接続され、互いに逆方向に直列接続されたダイオード素子1,6と、抵抗素子8の信号処理回路1側と接地端子3の間に接続された容量素子12とで構成される。

3. 发明专利

JP2017509141A 表面電荷に対して低減された感度を有する構造及び方法审中-公开
公开(公告)号：JP2017509141A
公开(公告)日：2017-03-30
申请号：JP2016544603
申请日：2015-01-16
申请人：アイディールパワーインコーポレイテッド , アイディールパワーインコーポレイテッド
发明人：リチャードエー．ブランチャード , リチャードエー．ブランチャード
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/732 , H01L29/739 , H01L29/78
CPC分类号： H01L29/0619 , H01L29/0615 , H01L29/0661 , H01L29/0692 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/402 , H01L29/404 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/735 , H01L29/7393 , H01L29/7397 , H01L29/747 , H03K17/66
摘要：本願は、バイポーラ導電を使用する両面パワー半導体デバイスに特に適用可能である改良を(より広く適用可能な発明に加えて)提供する。このクラスのデバイスにおいて、両面パワーデバイスのアクティブデバイス(アレイ)部分内のキャリアエミッション構造及び制御構造を形成する4つ(又はそれより多い)の半導体ドーピング構成要素のうちの2つ又は3つの半導体ドーピング構成要素をまた、両方の表面上でアクティブアレイの周りにフィールドリミティングリングを形成するのに、驚くほどに有利に使用し得ることを本発明者は認識した。最も好ましいことには、必ずしも全てではないが一部の実施形態において、1つの導電型の浅いインプラントが、他の導電型を有するウェルの表面をカウンタドープするのに用いられる。この浅いインプラントは、単独で、又は、同じ導電型の別の浅いインプラントと組合せられて、半導体材料の表面又は表面上で過剰な電荷の影響からウェルをシールドするように働く。

4. 发明专利

JPS61129866A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61129866A
公开(公告)日：1986-06-17
申请号：JP25059984
申请日：1984-11-29
申请人： Toshiba Corp
发明人： YASUDA SEIJI , ETSUNO YUTAKA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
CPC分类号： H01L29/72
摘要： PURPOSE:To produce transistors of microstructure and good accuracy by a method wherein impurities are introduced to the first region relatively small and the second region relatively large surrounding the first region by using the same insulation film mask. CONSTITUTION:The oxide film 2 formed on the main surface of a semiconductor substrate 1 is selectively opened by photo etching, thus forming a diffusion opening 21 for the second region formation and a diffusion opening 2b for the first region formation in the oxide film 2. Next, after the part outside the diffusion opening 2b is coated with a resist film 5, an emitter-forming impurity (n) is ion-implanted to the exposed substrate 1. Then, the resist film 5 is exfoliated, and a resist film 7 is formed on the oxide film 2 so as not to cover to the outer edge of the diffusion opening 2a. A base-forming impurity (p) is ion- implanted to the substrate surface in the diffusion opening 2a. Thereafter, the resist film 7 is removed, and an insulation film 8 is adhered over the whole surface and heat-treated, resulting the simultaneous formation of a base region 3 and an emitter region 4 in the substrate 1.
摘要翻译：目的：通过使用相同的绝缘膜掩模，通过其中杂质被引入第一区域相对较小的方法和围绕第一区域的较大的第二区域的方法来制造微结构的晶体管和良好的精度。构成：通过光蚀刻选择性地打开形成在半导体衬底1的主表面上的氧化物膜2，从而形成用于第二区域形成的扩散开口21和用于氧化物膜2中的第一区域形成的扩散开口2b。接着，在扩散口2b的外侧涂敷抗蚀膜5之后，向露出的基板1离子注入发射体形成杂质（n）。然后，剥离抗蚀剂膜5，将抗蚀剂膜7 形成在氧化物膜2上，以便不覆盖扩散开口2a的外边缘。基底形成杂质（p）离子注入到扩散开口2a中的衬底表面上。此后，除去抗蚀剂膜7，并且将绝缘膜8粘附在整个表面上并进行热处理，从而在基板1中同时形成基底区域3和发射极区域4。

5. 发明专利

JPS61123177A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61123177A
公开(公告)日：1986-06-11
申请号：JP24348984
申请日：1984-11-20
申请人： Fujitsu Ltd
发明人： HORIE HIROSHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
CPC分类号： H01L29/72
摘要： PURPOSE:To obtain a fine window for forming an emitter with high precision and excellent reproducibility by forming a coating consisting of polycrystalline Si or a metallic silicide onto a semiconductor substrate, on the surface whereof an insulating film is shaped, forming the window for shaping the emitter, applying the polycrystalline Si or metallic silicide film to a window section and removing others. CONSTITUTION:An SiO2 film 2 is formed onto an n type Si substrate 1, an Si3N4 film 3 is shaped onto the whole surface, a polycrystalline Si film 4 containing an impurity is formed onto the film 3, a photo-resist film 5 with an opening is shaped, and the film 4 is etched while using the film 5 as a mask to form a window 6 for shaping an emitter. A polycrystalline silicon film 7 is formed, and the film 7 is etched through anisotropic etching until the Si3N4 film 3 is exposed. Only the films applied to the film 4 facing the window 6 are left, and others are removed. Accordingly, the fine window 6 for shaping the emitter is formed with high precision and excellent reproducibility.
摘要翻译：目的：为了通过在半导体衬底上形成由多晶Si或金属硅化物组成的涂层，在绝缘膜成形的表面上形成高精度和优异的再现性的发光体的微细窗口，形成用于成形的窗口发射器，将多晶Si或金属硅化物膜施加到窗口部分并除去其它部分。构成：在n型Si衬底1上形成SiO 2膜2，在整个表面上形成Si 3 N 4膜3，在膜3上形成含有杂质的多晶Si膜4，具有开口成形，并且使用膜5作为掩模来蚀刻膜4，以形成用于使发射体成形的窗口6。形成多晶硅膜7，通过各向异性腐蚀蚀刻膜7直至暴露出Si 3 N 4膜3。只有施加到面向窗口6的胶片4上的胶片被留下，其它的被去除。因此，用于成形发光体的微小窗口6以高精度和优异的再现性形成。

6. 发明专利

JPS61102063A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61102063A
公开(公告)日：1986-05-20
申请号：JP22490784
申请日：1984-10-25
申请人： Fujitsu Ltd
发明人： HORIE HIROSHI
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/72 , H01L29/732
CPC分类号： H01L29/72
摘要： PURPOSE:To shrink a base region by leading out a base electrode from a base contact region formed around an emitter region through a conductive layer. CONSTITUTION:A composite layer consisting of an SiO2 layer 12, an Si3N4 layer 13 and an SiO2 layer 14 is shaped into a transistor Tr forming region on a base region 3B, and an Si3N4 layer 15 is applied onto the side surface of the composite layer. A field insulating layer 16 is formed through oxidation while using the layer 15 as a mask, and the layer 15 is removed. The layers 13, 12 are etched to expose the region 3B in the inner circumferential section of the Tr forming region. A poly Si layer 17 is applied onto the whole surface as a conductive layer, the layer 14 is removed, and the layer 17 is oxidized to shape an SiO2 layer 18. B in the layer 17 diffuses into the region 3B at that time, and a base contact region 3BC is formed. A poly Si layer 19 is applied as a conductive layer, and the layer 19 and the layer 13 and the layer 12 are etched to bore an emitter window 20.
摘要翻译：目的：通过引导基底电极从通过导电层形成在发射极区周围的基极接触区域收缩基极区域。构成：由SiO 2层12，Si 3 N 4层13和SiO 2层14构成的复合层成形为基极区域3B的晶体管Tr形成区域，并且在复合层的侧面上施加Si 3 N 4层15 。在使用层15作为掩模的同时通过氧化形成场绝缘层16，并且去除层15。蚀刻层13,12以暴露Tr形成区域的内周部分中的区域3B。多晶硅层17作为导电层施加到整个表面上，去除层14，并且层17被氧化以形成SiO 2层18.此时层17中的B扩散到区3B中，并且形成基极接触区域3BC。施加多晶硅层19作为导电层，并且蚀刻层19和层13以及层12以穿透发射器窗口20。

7. 发明专利

JPS6179254A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6179254A
公开(公告)日：1986-04-22
申请号：JP20057584
申请日：1984-09-27
申请人： Fujitsu Ltd
发明人： GOTO HIROSHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
CPC分类号： H01L29/72
摘要： PURPOSE:To obtain a fine bored window by forming a mask containing an Si3N4 film onto a poly Si layer on an Si substrate, introducing and oxidizing an impurity and removing an impurity non-introducing section by a formed oxide-film mask. CONSTITUTION:An n Si substrate 10 is isolated by an oxide film 12, poly Si 20, a thermal oxide film 21, and a CVDSi3N4 mask 22 are superposed, a photo-resist 23 is left on an emitter forming region, and the side surface of the Si3N4 22 is etched preferentially by selecting conditions. B ions are implanted by 10 /cm or more. When the resist 23 is removed and the remainder is oxidized, SiO2 25 is formed while an impurity is activated, the window of the film 25 is made narrower than a window by lithography accuracy, an emitter window is shaped on the inside of an ion implanting boundary 20a, and a section between an external base and an emitter is narrowed. Si3eN4 22 and SiO2 21 are etched by HF and SiO2 25 by KOH, a non-adding section 20b is removed preferentially, the surface is coated with CVDSiO2 28, films 26, 28 are left on the side wall of the window through PIE, and an internal base 30 and the emitter are formed. According to the constitution, the fine emitter window is obtained, and base-collector capacitance can be reduced.
摘要翻译：目的：通过在Si衬底上的多晶硅层上形成含有Si 3 N 4膜的掩模，通过形成的氧化物膜掩模引入和氧化杂质并去除杂质非导入部分，来获得细孔。构成：通过氧化物膜12，多晶Si 20，热氧化膜21和CVDSi 3 N 4掩模22叠置n

8. 发明专利

JPS6149471A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS6149471A
公开(公告)日：1986-03-11
申请号：JP17209484
申请日：1984-08-17
申请人： Sanyo Electric Co Ltd , Tokyo Sanyo Electric Co Ltd
发明人： TANAKA TADAHIKO , NOZAKI TSUTOMU
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
CPC分类号： H01L29/72
摘要： PURPOSE:To manufacture a base region and an emitter region finely, precisely and simply by using an oxidation-resistant film directly or indirectly and forming each region in a transistor through a self-alignment method. CONSTITUTION:A thin oxide film 2 is shaped onto the surface of a semiconductor substrate 1, and an oxidation-resistant film 3 is formed onto a region as an emitter in a transistor (Tr). A P type base contact region 4 is shaped through ion implantation while using the film 3 as a mask, and the region 4 is driven in through heat treatment. Accelerating voltage is increased from a pre-process, and a P type base region 5 is formed through ion implantation. The oxide film except a region in which the film 3 adheres is shaped thickly through selective oxidation while employing the film 3 as a mask. The film 3 is removed, and an N type emitter region 6 is formed in the region 5 through ion implantation. According to the method, each region in the Tr can be formed through a self- alignment system using the film 3 as the mask directly or indirectly when the film 3 is patterned.
摘要翻译：目的：通过直接或间接使用抗氧化膜，通过自对准方法在晶体管中形成每个区域，精细，精确和简单地制造基极区域和发射极区域。构成：在半导体基板1的表面上成形有薄的氧化膜2，在作为晶体管（Tr）的发射极的区域上形成耐氧化膜3。在使用膜3作为掩模的同时，通过离子注入成形P +型基极接触区域4，并且通过热处理驱动区域4。加速电压从预处理增加，通过离子注入形成P型基极区域5。除了膜3粘附的区域之外的氧化膜通过选择性氧化而成形为厚度，同时使用膜3作为掩模。除去膜3，通过离子注入在区域5中形成N +型发射极区域6。根据该方法，当膜3被图案化时，Tr中的每个区域可以通过直接或间接使用膜3作为掩模的自对准系统形成。

9. 发明专利

JPS6142955A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS6142955A
公开(公告)日：1986-03-01
申请号：JP16526884
申请日：1984-08-07
申请人： Nec Corp
发明人： MORIYAMA MASATOSHI , OHIRA MASAAKI
IPC分类号： H01L29/73 , H01L21/205 , H01L21/331 , H01L21/762 , H01L29/72
CPC分类号： H01L29/72 , H01L21/76202
摘要： PURPOSE: To obtain a transistor which has uniformly high emitter-collector breakdown voltage and high current gain by selectively forming an insulating film on the first epitaxial layer on a semiconductor substrate, then forming the second epitaxial layer, and forming an active element in the second layer surrounded by an insulating film.
CONSTITUTION: After an N type high density impurity layer 3 is formed in a P type silicon substrate 1, an N type impurity layer 4 is formed on the substrate 1. Then, a silicon oxide film 10 is formed, the film 10 is selectively etched and removed. Subsequently, an N type impurity layer 11 is formed on the film 10 and the layer 4, and a polysilicon layer 13 is formed on the silicon oxide film. Thereafter, the layer 11 is partly oxidized from the surface, a thin silicon oxide film 9 is formed, and a silicon nitride film 12 is formed on the film 9. Then, the film 12 is selectively etched and removed, and patterned. Further, a thick silicon oxide film 5 is selectively formed on the layer 11 using high pressure oxidation to the depth of the position of the film 10.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在半导体衬底上的第一外延层上选择性地形成绝缘膜，获得具有均匀高的发射极 - 集电极击穿电压和高电流增益的晶体管，然后形成第二外延层，并在第二外延层中形成有源元件层被绝缘膜包围。构成：在P型硅衬底1中形成N型高浓度杂质层3之后，在衬底1上形成N型杂质层4.然后，形成氧化硅膜10，选择性地蚀刻膜10 并删除。随后，在膜10和层4上形成N型杂质层11，在氧化硅膜上形成多晶硅层13。此后，层11从表面部分氧化，形成薄的氧化硅膜9，并且在膜9上形成氮化硅膜12.然后，选择性地蚀刻和去除膜12并进行图案化。此外，在层11上使用高压氧化选择性地形成厚的氧化硅膜5至膜10的位置的深度。

10. 发明专利

JPS60196971A Lateral type transistor 失效
标题翻译：横向型晶体管
公开(公告)号：JPS60196971A
公开(公告)日：1985-10-05
申请号：JP5301984
申请日：1984-03-19
申请人： Nec Corp
发明人： TAKANASHI MIKIO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To enable a high-gain zone width product and high-current gains by forming the other conductive type region in one conductive type semiconductor region and isolating the other conductive type region into an emitter region and a collector region by one conductive type high concentration region. CONSTITUTION:One conductive type epitaxial layer 8 is formed on the other conductive type semiconductor substrate 1, and isolated into a large number of island regions by the other conductive tupe isolation regions 9. The other conductive type regions are isolated by one conductive type high concentration regions, and collector regions 5b and emitter regions 5a are shaped. One conductive type high concentration regions 7 function as base regions, thus constituting lateral type PNP transistors. The base regions in the lateral type PNP transistors have controllability at a high degree because they are formed by diffusion or ion implantation and also have the high efficiency of charge injection from the emitter regions, thus easily obtaining desired high fT and high hFE.
摘要翻译：目的：通过在一个导电型半导体区域中形成另一个导电类型的区域，并通过一个导电类型的高浓度将另一个导电类型的区域隔离成发射极区域和集电极区域，来实现高增益带宽积和高电流增益地区。构成：在另一个导电型半导体衬底1上形成一个导电型外延层8，并通过其它导电元件隔离区9将其隔离成多个岛区。另一个导电类型区被隔离一个导电型高浓度区域和集电极区域5b和发射极区域5a成形。一个导电型高浓度区域7用作基极区域，从而构成横向型PNP晶体管。横型PNP晶体管中的基极区域由于通过扩散或离子注入形成而具有高度的可控性，并且还具有从发射极区域的电荷注入的高效率，因此容易获得期望的高fT和高hFE。

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