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1. 发明专利

JPS55107591A STAINLESS STEEL WIRE ROPE HAVING METAL FITTING AT END PORTION THEREOF 失效
公开(公告)号：JPS55107591A
公开(公告)日：1980-08-18
申请号：JP1289879
申请日：1979-02-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON MINIACHIYUA ROOPU KK , OKI ELECTRIC IND CO LTD , YAMURA SHINKOSEISAKUSHO KK
发明人： NISHIHATA MIKIO , MATSUNAGA KAZUO , SAKAMOTO CHIKAO , KIMURA TOORU , SHIRAFUJI MASAETSU
IPC分类号： B23K1/20 , D07B5/00 , D07B9/00

2. 发明专利

JPS55162898A DRIVING METHOD FOR PULSE MOTOR 失效
公开(公告)号：JPS55162898A
公开(公告)日：1980-12-18
申请号：JP6955579
申请日：1979-06-04
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , YAMURA SHINKOSEISAKUSHO KK , KUROSAWA TELECOMMUNICATIONS
发明人： GOTOU TAKU , KIMURA TOORU , HASHIMOTO TAKAO , KASAHARA TAKAAKI
IPC分类号： H02P8/14 , H02P8/16 , H02P8/00
摘要： PURPOSE:To decrease consumed power for obtaining the same mechanical output and reduce heating, by simultaneously selecting plural phase windings of a pulse motor and causing a current to flow forward through at least one phase winding while flowing backward through the other phase windings. CONSTITUTION:A voltage V1 is selected by a changeover switch S to drive transistors Q1-Q4, Qe in a rapid drive mode. At that time, a foward current flows through one only one of phase windings C1, C4 but no forward current flows through the others. In the first stage of the mode, the forward current flows through the winding C1 as V1-S-Qe-C1-D1-Q2-ground. A voltage V2 is selected by the changeover switch S to drive the transistors Q1-Q4, Qa-Qe in a slow drive mode. At that time, a forward current flows through one of the phase windings C1-C4 and a backward current flows through the others. In the first step of the mode, a current flows forward through the winding C1 but backward through the winding C3 as V2-S-Qa-C3-C1-D1-Q1-ground.

3. 发明专利

JPS5540824A WIRE ROPE 失效
公开(公告)号：JPS5540824A
公开(公告)日：1980-03-22
申请号：JP11178678
申请日：1978-09-13
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON MINICHIYUA ROOPU KK , YAMURA SHINKOSEISAKUSHO KK , OKI ELECTRIC IND CO LTD
发明人： NISHIHATA MIKIO , MATSUNAGA KAZUO , SAKAMOTO CHIKAO , KIMURA TOORU , SHIRAFUJI MASAETSU
IPC分类号： D07B1/06

4. 发明专利

JPS5274425A TYPE WHEEL 失效
公开(公告)号：JPS5274425A
公开(公告)日：1977-06-22
申请号：JP14947775
申请日：1975-12-17
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： NAKAGAWA MITSUO , KURIYAMA AKIUMI , OBARA WATARU , YOSHIDA AKINORI , SAITOU WATARU , KIMURA TOORU
IPC分类号： B41J1/32 , B41J1/24 , B41J1/54

5. 发明专利

JPS596534B2 JPS596534B2 - 失效
公开(公告)号：JPS596534B2
公开(公告)日：1984-02-13
申请号：JP4280
申请日：1980-01-07
申请人： Nippon Telegraph & Telephone
发明人： OKAMOTO SHIGEHARU , KOMAKI SHOZO , TAJIMA KOJIRO , KIMURA TOORU
IPC分类号： H04B7/08
CPC分类号： H04B7/084

6. 发明专利

JPS5698035A SPACE DIVERSITY RECEIVING SYSTEM 失效
公开(公告)号：JPS5698035A
公开(公告)日：1981-08-07
申请号：JP4280
申请日：1980-01-07
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： OKAMOTO SHIGEHARU , KOMAKI SHIYOUZOU , TAJIMA KOUJIROU , KIMURA TOORU
IPC分类号： H04B7/08
摘要： PURPOSE:To improve the frequency characteristics, by synthesizing the frequency components with which the signal level become minimum so as to secure the same phase when the signals supplied form the antennas are synthesized. CONSTITUTION:The signals supplied from the antennas 1 and 2 are synthesized by the synthesizing device 5 and then branched into two groups. Furthermore the signals of one group are branched into two parts to be applied to the frequency characteristics detecting circuit 10 and the frequency variable narrow-band pass filter 9. The frequency characteristics is detected at the circuit 10 for the signals after synthesizing to detect the frequency having the minimum level. Then a coincidence is secured between the frequency of the filter 9 and the detected frequency. Accordingly, only the signal component with which the frequency characteristics becomes minimum is applied to the wave detector 9 to ensure a synthesizing of the frequency components with the same phase.

7. 发明专利

JPS5460843A INFINITE PHASE SHIFTER 失效
公开(公告)号：JPS5460843A
公开(公告)日：1979-05-16
申请号：JP12723677
申请日：1977-10-25
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： OOMORI HIDEAKI , KOMAKI SHIYOUZOU , KIMURA TOORU
IPC分类号： H03H7/20 , H03C3/00 , H03H11/20 , H04B7/02
摘要： PURPOSE:To obtain a miniature infinite phase shifter featuring a reduced insertion loss by providing two pairs of variable phase shifters containing the finite phase shift amount and then switching these two pairs of phase shifters alternately under a fixed condition. CONSTITUTION:The infinite phase shifter consists of the following units: switch 3 to vary the distribution ratio of the signals supplied to signal input terminal 1; a pair of phase shifters 5 and 6 which are connected to each output of switch 3 with the finite variable range; and switch circuit 4 or compounder 8 which compounds the output of shifter 5 and 6 and then delivers the composite output to output terminal 2. In such phase shifter, the signal amplitude a and b which pass through shifter 5 and 6 are referred to as a and b with the phase difference theta between both signals respectively. And a switching action is given so that a fixed relation may be satisfied for a +b +2ab costheta. In that case, the phase shift amount of 5 and 6 can be controlled by application of the binary signal.

8. 发明专利

JPS5856294B2 JPS5856294B2 - 失效
公开(公告)号：JPS5856294B2
公开(公告)日：1983-12-14
申请号：JP4331078
申请日：1978-04-14
申请人： Nippon Telegraph & Telephone
发明人： KOMAKI SHOZO , OOMORI HIDEAKI , KIMURA TOORU
IPC分类号： H04L1/02 , H04B7/005 , H04B7/10
CPC分类号： H04B7/005

9. 发明专利

JPS5460820A PHASE SHIFTER FOR DIVERSITY SYSTEM 失效
公开(公告)号：JPS5460820A
公开(公告)日：1979-05-16
申请号：JP12723777
申请日：1977-10-25
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SAKAMOTO MASAYUKI , OOMORI HIDEAKI , KOMAKI SHIYOUZOU , KIMURA TOORU
IPC分类号： H03H11/20 , H04B7/08
摘要： PURPOSE:To use the local oscillator in common to the reception waves of two systems to simplify the constitution of the device as well as to solve the problem of the step-out, by branching off the output of one local oscillator into two parts and carrying out the frequency multiplication after making the branched output pass through the phase shifter featuring a small variable phase shift amount. CONSTITUTION:The reception waves of two systems are compounded with each corresponding local signal to obtain the two-system IF signals, and both signals are compounded together. In the phase shifter of such diversity system, the output of local oscillator 8 is divided into two and one of the branched output is supplied to phase shifter 14. Phase shifter 14 is constituted so that it may produce small phase shift amount less than 360 deg. according to the output voltage of phase detector 17, and the output signal is applied to first multiplying circuit 16. Then the output of circuit 16 is applied to frequency converter 4. The other side of the branched output is applied to second multiplying circuit 15, and the output is applied to frequency converter 3 after n-multiplication. The frequency conversion is given to the received two-system signals against the oscillation wave of local oscillator 8 to obtain the IF signal, and then the received two-system signals are compounded through compound circuit 7.

10. 发明专利

JPS5460819A DIVERSITY RECEIVING PHASE CONTROL SYSTEM 失效
公开(公告)号：JPS5460819A
公开(公告)日：1979-05-16
申请号：JP12723577
申请日：1977-10-25
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： OOMORI HIDEAKI , KOMAKI SHIYOUZOU , KIMURA TOORU
IPC分类号： H04B7/08 , H04B7/02
摘要： PURPOSE:To facilitate easy design and adjustment by constituting the phase control circuit with the digital element and thus to enhance the stability, secular change and control accuracy as well as to realize the common use of the phase control system with the reception device. CONSTITUTION:One of the reception waves of 2-system receives the phase inversion by the low frequency, and then the other wave or both waves is/are processed through the phase shifter. Then the both waves are compounded to detect the signal corresponding to the low frequency, and the phase shifter is controlled using the above detected signal as the phase difference signal to secure the coincidence of the phase for the reception waves. In such diversity reception device, sensing signal S1 extracted through AGC amplifier via divider circuit 4 and using signal S0 sent from clock oscillator 3 as the reference signal is applied to exclusive logical sum circuit 2 which supplies signal S1 via A/D converter 1. Furthermore, shift register 5 which supplies the output of circuit 1 is given reference signal S0 to process the output of circuit 2, output S5 of register 5 and the output of circuit 2 are applied to adder circuit 6, and the contents of reversible counter 7 is modified by output S6 of circuit 6.

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