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1. 发明专利

JPH09200879A NETWORK ACCESS SYSTEM 失效
公开(公告)号：JPH09200879A
公开(公告)日：1997-07-31
申请号：JP649296
申请日：1996-01-18
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： SAKURAI YOSHIO , KASE ICHIRO , SAITO KIYOSHI , OGAWA KAZUHIKO , NAKAYAMA HISAO
IPC分类号： H04J3/00 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To make it unnecessary to increase equipments in a public communication network, to eliminate the necessity of fare charge in the public communication network and to obtain an economical effect by directly connecting each subscriber's terminal equipment to a network such as a wide band LAN without passing an exchange. SOLUTION: Plural remote multiplex transmitters (RTs) 2 for storing plural terminals 1 are connected to a subscriber's line sorting module (LXM) 4 through multiplex communication lines 51. In the module LXM 4, a processor 46 receives '2B+D' channels from the terminals 1 through the RTs 2. The processor 46 sets up one Bchannel communication pass to be separated in each terminal 1 in a time division network (TDNW) based upon a previously determined condition and connects the communication pass separated in each terminal 1 to a multiplexing device (FH) 45. The FH 45 multiplexes B channels separated and connected correspondingly to each of plural terminals 1 and connects the multiplexed channel to a network through a private line 52.

2. 发明专利

JPH0951350A REMOTE MUTLIPLEX TRANSMISSION DEVICE 失效
公开(公告)号：JPH0951350A
公开(公告)日：1997-02-18
申请号：JP20104995
申请日：1995-08-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： OGAWA KAZUHIKO , KASE ICHIRO , SAITO KIYOSHI , NAKAYAMA HISAO , SAKURAI YOSHIO
IPC分类号： H04J14/00 , H04B10/27 , H04J14/04 , H04J14/06 , H04L12/12 , H04L12/28 , H04L12/44 , H04L12/46 , H04L12/66 , H04M3/00 , H04B10/20
摘要： PROBLEM TO BE SOLVED: To flexibly correspond to the fluctuation in various conditions of a stored subscriber terminal by introducing a hub as hardware configurating LAN and providing a processor and a bus corresponding to respective terminal equipmetns. SOLUTION: In HUB 5, a digital multiplex separation circuit 23 is connected to an interface 51, an ISDN terminal equipment 82 to the other interface 5n through an office channel unit 32 and a private line 96 and a multiplex communication line 95 are connected to the other interfaces 61 and 61. Since a personal computer as the ISDN terminal equipment 82 is connected through the interface 5n, the personal computer can be used as the input device of a prcoessor 70. Since the hub(HUB) 5 can freely be rewritten by an input device, a remote multiplex device incorporating the hub 5 is provided with a function and a constitution abundant in flexibility.

3. 发明专利

JPH0210961A TRANSMISSION SYSTEM OF DIAL SIGNAL FOR CONFIRMING CALLER 失效
公开(公告)号：JPH0210961A
公开(公告)日：1990-01-16
申请号：JP16197488
申请日：1988-06-28
申请人： MEISEI ELECTRIC CO LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： KATSUYAMA KAZUO , KANO TAKASHI , SAKURAI YOSHIO
IPC分类号： H04M3/60 , H04M3/64
摘要： PURPOSE:To reduce work man-hour of operation of caller subscriber number confirmation and to decrease the occurrence of an error by providing a means translating a signal coming to a line into information including a high-order digit number of the number to be sent to the line for confirming a caller to a control circuit. CONSTITUTION:The control circuit 8 is provided with a means translating a signal coming to an incoming line into the information including a high-order digit number of the number to be sent to a line for confirming a caller. For example, when an incoming call comes to an incoming line 1-1, a switch 5 is controlled and connected to a reception terminal equipment 7-1, the toll station number and the local station number of the line 1-1 are translated and stored in a storage device 9 and displayed on the reception terminal equipment 7-1. That is, in the case of confirming a caller, when the telephone number of the caller is 03-509-2111, the number 3509 is stored in the device 9 and displayed on the terminal equipment 7-1, the terminal operator confirms the said digit, inputs the lower 4-digit and the number input processing is applied via the circuit 8. Thus, the operation of the caller subscriber number confirmation by the operator of the reception terminal equipment is reduced and mis-operation is reduced.

4. 发明专利

JPH0951310A OPTICAL COMMUNICATION NETWORK 失效
公开(公告)号：JPH0951310A
公开(公告)日：1997-02-18
申请号：JP20103395
申请日：1995-08-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： OGAWA KAZUHIKO , KASE ICHIRO , SAITO KIYOSHI , NAKAYAMA HISAO , SAKURAI YOSHIO
IPC分类号： H04B10/27 , H04B10/272 , H04B10/275 , H04L12/42 , H04L12/43 , H04B10/20
摘要： PROBLEM TO BE SOLVED: To reduce cost on remote multiplex transmission devices and to reduce equipment cost by connecting plural remote multiplex transmission devices together in a loop with an optical transmission line. SOLUTION: The remote multiplex transmission devices 1-3 which store more than one subscriber terminals T1-T3 and mutually convert electric signals and optical signals, subscriber distribution module 9 as an exchange station device that stores plural transmission devices 1-3 and an exchange 10 are provided. The transmission devices 1-3 are mutually connected to the subscriber distribution module 9 by the optical transmission line 94. The transmission devices 1-3 are connected in a loop by the optical transmission lines L1-L4. One repeating device 7 is interposed in the loop-like optical transmission lines L1-L4. The optical transmission line 94 connecting the repeating device 7 and the subscriber distribution module 9 is provided separately from the loop-like optical transmission lines L1-L4. Thus, the remote multiplex transmission devices 1-3 are constituted to be smaller and lighter compared to the repeating device 7.

5. 发明专利

JPS60204054A INTERRUPTION CONTROL SYSTEM 失效
公开(公告)号：JPS60204054A
公开(公告)日：1985-10-15
申请号：JP5906084
申请日：1984-03-27
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： KOMATSUBARA TSUTOMU , MIKI SHIYUUJI , YAMADA TAKAHIKO , SAKURAI YOSHIO
IPC分类号： G06F9/22 , G06F9/48 , G06F13/24
摘要： PURPOSE:To improve the efficiency and the flexibility by causing always a microprogram interruption when an interruption request occurs and executing processings of interruption control, start of external devices, etc. with a microprogram. CONSTITUTION:When an external device 1 lights an interruption request indicator 4 in an interruption circuit 3, the microprogram interruption is generated, and the microprogram starts execution of an interruption control routine 9 in a control memory 8 of a microprogram executing circuit 7. In this interruption control routine 9, interruption request indicators 4 in the interruption circuit 3 are first read out, and a factor issuing a request out of plural factors is discriminated. The interruption request indicator 4 is reset simultaneously with this read-out. Next, an external device start routine 10 is executed in accordance with the turn-on or off states of chain processing request indicators 11 or it is discriminated whether interruption is possible or not by interruption mask indicators 12 to start the interruption processing due to machine instructions.

6. 发明专利

JPS60174963A ELECTRONIC PACKAGE TESTING CIRCUIT 失效
公开(公告)号：JPS60174963A
公开(公告)日：1985-09-09
申请号：JP3027084
申请日：1984-02-22
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： TAKI YOSHIHARU , WAKIMURA YOSHIAKI , SAKURAI YOSHIO , URUSHIBARA TETSUO
IPC分类号： G01R31/28 , G01R31/316 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PURPOSE:To enable an operation test of a logic circuit by arranging an input terminal to be used only for operation test on an LSI circuit and a circuit which provides an output from the input terminal with a higher impedance of all of the output terminals and bi-directional terminals of the integrated circuit to electrically cut the logic circuit off the LSI circuit. CONSTITUTION:Output terminals 7 and 8 of an integrated circuit 9 are connected to perform an operation test of a combination logic circuit 14 having an input terminal 15 and to be more specific, the operation of an inverter 17, an AND circuit 18 and a NAND circuit 19 is checked. So, the outputs of AND circuits 1 and 2 go to the L level by setting the input terminal 6 of the integrated circuit 9 at the H level. Therefore, as tristate gates 3 and 4 are turned to a high impedance, the output terminal 7 and the bi-directional output terminal 8 also give a high impedance. This electrically cuts the combination logic circuit 14 in an electronic package off the integrated circuit 9 thereby facilitating the operation test of the logic circuit.

7. 发明专利

JPS57109022A CONTROL SYSTEM FOR COMMON SIGNAL BUS 失效
公开(公告)号：JPS57109022A
公开(公告)日：1982-07-07
申请号：JP18559580
申请日：1980-12-26
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： SAKURAI YOSHIO , YAMADA SHIGEKI
IPC分类号： G06F13/30 , G06F9/46 , G06F13/362
摘要： PURPOSE:To realize application to even an input and output controller which requires high-speed data transfer by minimizing the processing interruption of a CPU, by limiting the processing interruption to only the time when the CPU uses a common signal bus. CONSTITUTION:A CPU1 is equipped with a main storage device 2 and an input and output controller 3 both connected to a common signal bus 4. Once the CC use display FF14 of the CPU1 is set, the CPU1 gains the right to use the bus 4 and inhibits a use request 5 from the controller 3 while a signal for CC in-use display 52 is outputted. Then, when the CPU1 does not use the bus 4 any more, an external use permission FF54 is set and a signal for use permission 6 is supplied to the controller 3. Even if a use request 11 is generated by the CPU1 during the period, the FF14 is inhibited from being set because the FF52 is set. As the use request 5 for the bus 4 from the controller 3 ends, the FF52 is reset and the FF14 is set, giving the CPU1 the right to use the bus 4.

8. 发明专利

JPS5798030A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5798030A
公开(公告)日：1982-06-18
申请号：JP17472280
申请日：1980-12-12
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： ICHIURA NOBORU , WAKIMURA YOSHIAKI , SAKURAI YOSHIO , FURUKAWA KAZUO , URUSHIBARA TETSUO
IPC分类号： G06F13/12 , G06F12/04 , G06F13/28
摘要： PURPOSE:To improve the capability of processing data by transferring data in any given location and in any given number on the main storage specified the byte location in the starting word and the byte location in the last word by a program, to an input/output device. CONSTITUTION:The location of a byte in the starting word and that in the last word both of which are specified by a channel controlling word CCW are assigned by a program to a data channel 13 between a main storage device 12 and an I/O device 14 or between the devices 12. Then, data in any given location and in any given number on the device 12 is transferred to the I/O device. Thereby the terminal location of data transfer can be matched with the boundary of a word by the program, which improves the capability of processing data.

9. 发明专利

JPS5448446A MEMORY UNIT CONTROL SYSTEM 失效
公开(公告)号：JPS5448446A
公开(公告)日：1979-04-17
申请号：JP8158277
申请日：1977-07-08
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： SHINTANI HIROSHI , ISHIDA KAZUO , SAKURAI YOSHIO , URUSHIBARA TETSUO
IPC分类号： G06F12/06 , G11C8/18
摘要： PURPOSE:To enable the control of memory different in speed and to simplify the unit, by using shift registers, in the information processing system including a plurality of memory devices different in speed. CONSTITUTION:In the information processing system including the processor interpreting and executing the program stored in the memory devices MMa to MMd which are different in speed and the memory control cirucit external the processor or internal it, the memory unit control circuit is provided with shift registers 19 shifting toward 1 at all times. Further, at the initiation of access of the memory units, the digit location set section inputting the memory access initiation information to the digit location for different registers corresponding to the speed of the memory units MMa to MMd is constituted, and the short circuits 7a to 7d selecting and shortening the digit location and the memory start signal forming circuit 3 and AND circuits 12, 14 to 17 are provided.

10. 发明专利

JPS5344133A DATA CHANNEL DEVICE 失效
公开(公告)号：JPS5344133A
公开(公告)日：1978-04-20
申请号：JP11969476
申请日：1976-10-04
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： SAKURAI YOSHIO , YAMADA TAKAHIKO , TAKASE JIYUNICHI , SHIYOUDA AKIO , AWAJI TOSHIO
IPC分类号： G06F11/30 , G06F3/00 , G06F13/00
摘要： PURPOSE:The method is provided which supervises the response time using the general timer inside a central control unit, so that the execution time of an inputoutput unit starting instruction and the response time of a sub-channel equipment can be supervised without installing the special timer for the time supervision of the instruction.

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