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    • 7. 发明专利
    • COMPLEMENTARY SEMICONDUCTOR DEVICE
    • JPS6089957A
    • 1985-05-20
    • JP19752483
    • 1983-10-24
    • NIPPON TELEGRAPH & TELEPHONE
    • SAKURAI TETSUTADAOONO AKIKAZUIZUMI KATSUTOSHI
    • H01L27/08H01L21/762H01L27/092
    • PURPOSE:To obtain a C-MOS element which shows a high resistance voltage, low power consumption and has high packing integration density by providing a plurality of islands insulated and separated by insulation films in a support substrate, providing an island having no insulation film at the bottom surface to at least one of such islands, forming any of at least one P channel MOS element in such island, and forming a channel MOS element having conductivity type different from said MOS element in this island where the insulation film exists at the bottom surface. CONSTITUTION:A couple of N type island regions 8 of which entire part is covered with an insulation film 6 are provided on the P type support substrate 7, a second island region 8' where only side wall is surrounded by the insulation film 6 is formed between the regions 8, and both N type source region 92 and drain region 102 are provided herein, thereby completing an N channel MOS element 16. A couple of P type source regions 91 and drain regions 101 are respectively provided to the one second island region 8, forming a couple of P channel MOS elements 15. On the other hand, the P type base region 94 and the N type emitter region 93 are provided in the other region 8, thus completing a bipolar type N-P-N transistor element 18.
    • 9. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPS57143842A
    • 1982-09-06
    • JP2921281
    • 1981-02-28
    • NIPPON TELEGRAPH & TELEPHONE
    • SAKURAI TETSUTADAKATOU KOUTAROU
    • H01L21/306H01L21/31H01L21/762
    • PURPOSE:To make the main surface of semiconductor element region accurately flat when a substrate is removed after the epitaxial growth of an element region layer is made on a semiconductor single crystal substrate and the respective regions are separated by etching and an insulation layer and a supporting layer are formed. CONSTITUTION:Thin impurity diffusion regions 33 are formed on the surface of a semiconductor single crystal substrate 32. The epitaxial growth of a semiconductor layer 35 which forms element regions are made on the substrate and the respective regions are separated by etching. After an insulation film 39 and a poly- Si supporting layer 40 are formed, etching is carried out from the surface of the substrate 32. With the progress of the etching, the diffusion layers 33 are exposed and difference of etchig speed is caused by differnce of impurity density and so forth. When the differnce in level is generated by the difference of etching speed, the surface is polished and the main surface 45 of the semiconductor layer 35 which forms element regions 44 is made accurately flat, so that the element regions 44 can be formed to the specified thickness in parallel with the substrate surface.
    • 10. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPS57106066A
    • 1982-07-01
    • JP18129580
    • 1980-12-23
    • NIPPON TELEGRAPH & TELEPHONE
    • SAKURAI TETSUTADAKATOU KOUTAROUOONO AKIKAZU
    • H01L21/8226H01L27/02H01L27/082
    • PURPOSE:To enable to form low withstand voltage elements on the same substrate with a high withstand voltage element without damaging characteristic of the latter in a semiconductor device by a method wherein after a part of a protective film formed on an epitaxial layer is removed selectively, the second epitaxial layer is formed thereon. CONSTITUTION:The first N type buried layer 5 is formed on a P type semiconductor substrate 4. Then the first N type epitaxial layer 7 is formed. P type isolation diffusion layers 10 are formed in the layer 7. Openings are formed selectively in the protective film 14 generated during formation of the layer 10, the second N type buried layers 8 are formed, and the second N type epitaxial layer 9 is formed thereon. At this time, the layer 9 being made to grow at the part in which the film 14 is existing grows as a polycrystalline Si layer 15, and the layer 9 being made to grow at the part in which the film 14 is not existing grows as a single crystal Si layer 16. After then, then necessary part of the layer 9 is made to be reserved selectively to form the low withstand voltage elements, and the high withstand voltage element is formed in the isolation region of the layer 7 in which the layer 8 is not formed. Accordingly because thickness and concentration of impurity of the epitaxial layer to form the low withstand voltage element and the high withstand voltage element can be set for both independently, the desired characteristic can be obtained.