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1. 发明专利

JPH0786107A STICKING METHOD FOR WAFER 失效
公开(公告)号：JPH0786107A
公开(公告)日：1995-03-31
申请号：JP22919093
申请日：1993-09-14
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT ELECTRONIC TECH
发明人： IMAI KAZUO , SHIMOKUCHI NOBUYUKI , SAKURAI TETSUTADA
IPC分类号： H01L21/02 , H01L27/12
摘要： PURPOSE:To provide a method for sticking wafers in which the yield and quality are enhanced by embodying a controlled wafer profile. CONSTITUTION:The method for sticking first and second wafers 21, 22 comprises a step for preparing the first wafer having convex bonding surface and the second wafer having concave bonding surface, a step for machining the bonding surface of the first wafer 21 to have average radius of curvature shorter than that of the second wafer 22, and a step for bonding the first and second wafers 21, 22.

2. 发明专利

JP2001313416A POROUS SILICON LIGHT-EMITTING ELEMENT AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001313416A
公开(公告)日：2001-11-09
申请号：JP2000128780
申请日：2000-04-28
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT AFTY CORP
发明人： TAKAHASHI MITSUTOSHI , IMAI KAZUO , KAMOSHITA KAZUYOSHI , KOSHIDA NOBUYOSHI , OIKAWA HIDEO
IPC分类号： H01L33/34 , H01L33/36 , H01L33/00
摘要： PROBLEM TO BE SOLVED: To provide a porous silicon light-emitting element in which changes with the passage of time in a luminous intensity is prevented and to provide its manufacturing method. SOLUTION: The porous silicon light-emitting element has a structure, where the region in a part on the surface of a heavily doped silicon single-crystal substrate 1 is made porous, a porous layer 2 is formed, a transparent electrode 4 is provided in a region at the inside of the region of the porous layer, and the single-crystal silicon substrate which is exposed on the surface, the porous layer and the transparent electrode are covered with an electron cyclotron resonance(ECR) sputtered and deposited silicon film or a silicon nitride film, or they are covered with the ECR plasma deposited silicon oxide film or a silicon nitride film 3. The film is manufactured at 200 deg.C. Consequently, it is possible to prevent a change, such as the desorption of hydrogen atoms which terminate the dangling bond on the surface of porous silicon, and a drop in the luminous intensity can be prevented.

3. 发明专利

JPH10321617A THIN FILM FORMATION METHOD AND THIN FILM FORMATION DEVICE FOR THE SAME 失效
公开(公告)号：JPH10321617A
公开(公告)日：1998-12-04
申请号：JP12531597
申请日：1997-05-15
申请人： CATALYSTS & CHEM IND CO , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAJIMA AKIRA , TONAI ATSUSHI , MURAGUCHI MAKOTO , KOMATSU MICHIO , MACHIDA KATSUYUKI , KURAKI OKU , IMAI KAZUO
IPC分类号： H01L21/3205 , B05D1/28 , H01L21/00 , H01L21/31 , H01L21/316 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To provide a continuous thin film formation method which can form a flattened thin film on a board such as a semiconductor wafer continuously and stably at a low cost, can avoid deterioration of quality due to attaching and inclusion of impurities to a thin film and aged deterioration of a thin film and is applicable also to a large board, and a thin film formation device for it. SOLUTION: The method has an application liquid supply device 6 for supplying thin film formation application liquid to a surface of a transfer roll 2, a transfer device 4 with the transfer roll 2 wherein thin film formation application liquid supplied from the application liquid supply device 6 is applied to a surface thereof, and a transfer thin film 8 is formed and a board carrier device 16 for carrying a board 9 whereon a thin film is to be formed below a transfer roll continuously. In the process, the transfer device 4 brings a transfer roll surface wherein a transfer thin film is formed to pressure contact with a surface of a board carried by the board carrier device 16, and transfers a transfer thin film formed in a surface of a transfer roll surface to a board surface.

4. 发明专利

JPH08125187A METHOD AND SYSTEM FOR FABRICATING MOS TYPE SEMICONDUCTOR DEVICE HAVING SOI STRUCTURE 失效
公开(公告)号：JPH08125187A
公开(公告)日：1996-05-17
申请号：JP25812394
申请日：1994-10-24
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： IMAI KAZUO , MIURA KENJI , AOKI TAKAHIRO
IPC分类号： H01L21/336 , H01L29/786
摘要： PURPOSE: To suppress deterioration of the performance of a transistor due to increase in the capacity of gate electrode at the time of formation of a body contact region. CONSTITUTION: A source region 6 connected with a source electrode 10 and a drain region 7 connected with a drain electrode 11 are formed on a silicon layer 16 overlying an insulation film 15 on the opposite sides of a channel region 9 connected with a body contact region 8. The body contact region 8 is connected with a body contact electrode 12 and a gate electrode 5 is formed through an insulation film 18, thicker than a gate insulation film 4, on the channel region 9 and on a part of the gate insulation film 4 and the body contact region 8.

5. 发明专利

JPH07221314A MOS SEMICONDUCTOR DEVICE HAVING SOI STRUCTURE 失效
公开(公告)号：JPH07221314A
公开(公告)日：1995-08-18
申请号：JP2759794
申请日：1994-02-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MIURA KENJI , AOKI TAKAHIRO , IMAI KAZUO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
摘要： PURPOSE:To install a body contact area so that the area can be applied to a fine gate without requiring any high matching accuracy, can have a bidirectional property, and can be also applied to the layout peculiar to the logic LSIs. CONSTITUTION:An body contact area 5 composed of a p -type impurity area is formed on the same line together with a source area 3 and drain area 4 so that the area 5 cannot come into contact with the source area 3 and drain area 4 which are composed of n -type impurity diffusion layers, but separated from the areas 3 and 4.

6. 发明专利

JPH053182A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH053182A
公开(公告)日：1993-01-08
申请号：JP17885691
申请日：1991-06-24
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKIMOTO MISAO , KIMIZUKA MASAKATSU , IMAI KAZUO
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To enable a pattern to be sharply lessened in dimensional error so as to obtain a polycrystalline silicon gate element of high accuracy by a method wherein a thin silicon oxide film formed at a low temperature is used as an etching mask. CONSTITUTION:In a method of manufacturing a semiconductor device, where an amorphous silicon film 53 is deposited on a substrate 51 and then selectively etched using a mask pattern formed on the film 52, and the substrate 51 is thermally treated to turn the amorphous silicon film 53 polycrystalline, a thin silicon oxide film 54 which is formed at a low temperature at which an amorphous silicon film is not turned polycrystalline is used as the mask pattern formed on the amorphous silicon film 53.

7. 发明专利

JPH04355931A MIS TYPE FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04355931A
公开(公告)日：1992-12-09
申请号：JP18347291
申请日：1991-06-28
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KURAKI OKU , IMAI KAZUO , MORIMOTO TAKASHI , KONAKA NOBUNORI
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To enable fine patterns to be formed by a method wherein a source electrode formation region and drain electrode formation region respectively connecting to a source region and a drain region are formed in an element formation region and then the impurities developing a second conductivity type are led into said formation regions respectively from a source electrode layer and a drain electrode layer so that fine patterns may be formed. CONSTITUTION:A source electrode formation region 22S and a drain electrode formation region 22D respectively connecting to a source region 6S and a drain region 6D are formed in an element formation region 2. Next, said regions 22S and 22D can be formed into fine patterns by leading the impurities developing P type into said regions 22S and 22D respectively from a source electrode layer 15S and a drain electrode layer 15D. Furthermore, said fine patterns can afford to make at least an alignment allowance between the source electrode formation region 22S and an element separation insulating film 3 as well as the same alignment allowance between the drain electrode formation region 22D and the element separation insulating film 3.

8. 发明专利

JPH0415950A COMPLEMENTARY FIELD-EFFECT SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0415950A
公开(公告)日：1992-01-21
申请号：JP11768790
申请日：1990-05-09
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MIYAKE MASAYASU , UGA KAMIMORI , IMAI KAZUO
IPC分类号： H01L27/092 , H01L21/265 , H01L21/8238
摘要： PURPOSE:To obtain a complementary field effect semiconductor device in which a leakage current is suppressed by disposing a crystal defect layer generated upon recrystallization of an amorphous layer at a deeper position than a depleted layer extended from a PN junction between a P-well or N-well and a substrate into the substrate. CONSTITUTION:A depleted layer of a junction between a P-well 5, an N type buried diffused layer 2 and an N-well 6, a junction between a source and a drain is extended, but since the depleted layer of the source, drain is disposed in the P-well, a crystal defect layer 7 generated upon formation of amorphous state does not exist therein, and does not affect an influence to the junction characteristics of the source, the drain. The depleted layer of the well junction is extended into the well 5, the well 6 and the layer 2, but the depth W1 of the layer 7 is set deeper than the depth (depth of the deeper depleted layer end) W2 of the depleted layer end extended from the well junction into the layer 2. The layer 7 does not exist in the depleted layer of a well junction and does not affect the junction characteristics of the well junction.

9. 发明专利

JPH0379903B2 失效
公开(公告)号：JPH0379903B2
公开(公告)日：1991-12-20
申请号：JP4143680
申请日：1980-03-31
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： IMAI KAZUO , YUKIMATSU KENICHI , MIZUNO TOSHIRO
IPC分类号： H04L5/22 , H04L25/08 , H04L25/40

10. 发明专利

JPH03276731A MANUFACTURE OF FIELD-EFFECT TYPE TRANSISTOR 失效
公开(公告)号：JPH03276731A
公开(公告)日：1991-12-06
申请号：JP7795990
申请日：1990-03-27
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MIYAKE MASAYASU , IMAI KAZUO
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To make it possible to provide high function and miniaturization by forming a second source region part and second drain region part which are connected to a first source region part and a first drain region part, respectively, at the parts deeper than the first region parts. CONSTITUTION:A first source region part 22 and a first drain region part 23 wherein p-type impurities are diffused are formed through insulating layers 17 and 18 from impurity containing layers 15 and 16, respectively, in regions beneath the insulating layers 17 and 18 by heat treatment in a semiconductor substrate 1. P-type impurities from an impurity containing layer 21 are diffused into regions 19 and 20. A second source region part 24 and a second drain region part 25 are connected to first region part and formed with the impurity containing layer 21. A source electrode layer 26 and a drain electrode layer 27 which are connected to the second source region part 24 and the second drain electrode region 25, respectively, are formed with the impurity containing layer 21. At the same time, an insulating layer 5' is exposed to the outside.

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