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    • 3. 发明专利
    • MULTIPLEX TRANSMISSION SPEED DATA COMMUNICATION SYSTEM
    • JPH02108344A
    • 1990-04-20
    • JP26056888
    • 1988-10-18
    • NIPPON TELEGRAPH & TELEPHONE
    • MAEKAWA EIJI
    • H04L29/08H04L7/00H04L12/40
    • PURPOSE:To allow plural pieces of sub-equipment to efficiently communicate through a common transmission path with main equipment by possessing a device to supervise a signal on a common outgoing transmission line and a device to control the sending of the signal to a common incoming transmission line by means of the sub-equipment, and automonously judging the propriety of communication. CONSTITUTION:Sub-equipment 2 to have a transmission speed different from that of the signal on a common outgoing transmission line 11 as the inherent transmission speed does not send a detecting signal from a signal detecting part 13, and since it does not sends a coincident signal from a speed conicidency detecting part 19, it does not transmits the signal to a common incoming transmission line 12, and the signals at the different transmission speeds do not collide on the line 12. Further, when the signal exists on the line 11 and the transmission speed of the signal corresponds to the transmission speed of the self-sub- equipment, the sub-equipment 2 sends the detecting signal from its detecting part 13, and since the consistent signal is sent from a detecting part 19, the equipment 2 can sends the signal onto the line 12, and the communication at the same speed is attained in the common transmission line. The propriety of the communication through the transmission line can be autonomously judged by the equipment 2 by sending a transmission stop signal 21 from a signal transmission control part B 20 to a main circuit part 16 by the device 2.
    • 4. 发明专利
    • PHASE COMPARATING CIRCUIT FOR CMI SIGNAL AND TIMING CLOCK
    • JPH01205620A
    • 1989-08-18
    • JP3019988
    • 1988-02-12
    • NIPPON TELEGRAPH & TELEPHONE
    • MAEKAWA EIJIKAKINUMA TAKAMAOGATA YOSHIFUMIUNO KOJI
    • H03K5/26
    • PURPOSE:To generate phase difference information between a CMI(Coded Mark Inversion) signal with an optional period and a timing clock, without generating information other than the phase difference information and zero information and without resetting the circuit constant in response to the period by constituting the circuit except a differential amplifier by logic circuits only. CONSTITUTION:A 1st exclusive OR output circuit 3 is realized by an exclusive OR gate EXE, and a 2nd exclusive OR output circuit 4 consists of the exclusive OR gate EXE and an inverter INV, a 1st pulse generating circuit 5, a 1st pulse generating circuit 5, a pulse elimination circuit 11 and a pulse addition circuit 14 are constituted by logic circuits only. Then a circuit 17 outputting a difference between two output signals 15, 16 of the pulse addition circuit 14 corresponding to output signals 7, 8 of the 1st and 2nd exclusive OR output cirrhosis 3, 4 is realized by a differential amplifier AMP. Thus, the phase difference information between the CMI signal with an optional period and the timing clock is generated without generating the phase difference information and the information except the zero information and without resetting the circuit constant in response the period.
    • 10. 发明专利
    • PHASE COMPARING CIRCUIT
    • JPH02152319A
    • 1990-06-12
    • JP30648888
    • 1988-12-02
    • NIPPON TELEGRAPH & TELEPHONE
    • KAKINUMA RIYUUMAMAEKAWA EIJI
    • H03K5/26H03L7/085
    • PURPOSE:To shorten a synchronous pulling-in time and to generate phase difference information by obtaining an exclusive logical sum between a timing clock at the change point of an input signal and the identifying signal of a logical level, and executing phase comparison between this exclusive logical sum and the input signal. CONSTITUTION:The logical level of a timing clock 102 at the rising point of an input signal 101 is identified by a D-FF1 and an identified output signal 103 and the clock 102 are outputted as an exclusive logical sum signal 104 by an EX-OR 2. The signal 104 and input signal 101 are outputted as an exclusive logical signal 105 by an EX-OR 3. The signal 105 is passed through a NOT gate 4 and defined as a logical refusing signal 106. For the signals 105 and 106, a difference signal 107 of those signals is obtained as a phase comparing signal by a differential amplifier 5. As a result, an instable pulling-in phase is changed to a stable pulling-in phase.