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1. 发明专利

JPS5323208A RECTIFIERRDETECTOR CIRCUIT 失效
公开(公告)号：JPS5323208A
公开(公告)日：1978-03-03
申请号：JP9704576
申请日：1976-08-16
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： HASHIZUME YUKINAO , USUDA SHIYOUGO , IWATA ATSUSHI , HASEGAWA KOUICHI , TAKAOKA KAZUHIKO , OSAJIMA MASAHIRO
IPC分类号： H04Q1/45 , H04L27/26 , H04Q1/453
摘要： PURPOSE:At a multi-frequency signal receiver, etc., the threshold value of an arithmetic amplifier for detection after the operation starting of rectifierdetector circuit is lowered and the control is operated by timing signals, thereby detecting signals stably.

2. 发明专利

JPS5312207A MULTIIFREQUENCY SIGNAL RECEIVER 失效
公开(公告)号：JPS5312207A
公开(公告)日：1978-02-03
申请号：JP8593476
申请日：1976-07-21
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： USUDA SHIYOUGO , IWATA ATSUSHI , HASEGAWA KOUICHI , TAKAOKA KAZUHIKO , KATAOKA MUTSUO , SASAHARA YUUJIROU
IPC分类号： H04Q1/45 , H04L27/26 , H04Q1/453
摘要： PURPOSE:To improve the SN ratio and to obtain an output of the same timing in order to prevent the malfunction, by controlling both the detector and the output control circuit using the timer circuit output for the common threshouls voltage.

3. 发明专利

JPS5698091A MULTIIFREQUENCY SIGNAL RECEIVER 失效
公开(公告)号：JPS5698091A
公开(公告)日：1981-08-07
申请号：JP79280
申请日：1980-01-08
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： HIRANO KAZUNARI , NAKAMURA MASANORI , IWASE YASUMASA , SHIRAISHI YOSHIKATSU , TAKAOKA KAZUHIKO , SASAHARA YUUJIROU
IPC分类号： H04Q1/45 , H04L27/26 , H04Q1/453
摘要： PURPOSE:To eliminate the disturbing noise, by identifying whether the level of the reception signal is within a range of prescribed stepped level, transmitting the output after the reception signal was comfirmed offective as the multi-frequency signal and then excerising a level control only over the undesired circuit noise. CONSTITUTION:The level identifying circuit 9 indentifies whether the level of the reception signal supplied to the buffer amplifier 1 is within a prescribed stepped level range. The logic circuit 12 supplies the reception signal via the low-group identifying circuit 6 and the high-group identifying circuit 10 and transmits the output when approving the effectiveness of the received signal as the multi-frequency signal. Then the level range identified by the comparators C1-C4 is stored in the momories M1-M4 each of the circuit 9 at the moment when the output is transmitted from the circuit 12. At the same time, the rear edge of the received multi-frequency signal is detected by the mono-multi 15, and the memories M1-M4 are reset after a fixed time. Then the variable attenuator circuit 4 is controlled via the relays R1-R4 and in accordance with the state of the memories M1-M4 to perform the level control. Thus the disturbance noise can be eliminated.

4. 发明专利

JPH04105456A FACSIMILE EQUIPMENT 失效
公开(公告)号：JPH04105456A
公开(公告)日：1992-04-07
申请号：JP22495290
申请日：1990-08-27
申请人： HITACHI LTD
发明人： KOMATSU MASAYUKI , TAKAOKA KAZUHIKO , YOKOSUKA YASUSHI
IPC分类号： H04N1/00
摘要： PURPOSE:To simplify the circuit constitution, to make the equipment small and to reduce the cost by employing one and same hardware so as to implement a read function, a recording function and a transmission function. CONSTITUTION:When a picture data is sent, a program to realize a read function is selected and executed and then a program to realize a transmission function is selected and executed. When a picture data is received, program to realize the transmission function is selected and executed and then a program to realize a recording function is selected and executed. When a picture data is copied, a program to realize the read function is selected and executed and then a program to realize the recording function is selected and executed.

5. 发明专利

JPH01194613A AUTOMATING EQUALIZER INITIALIZING SYSTEM 失效
公开(公告)号：JPH01194613A
公开(公告)日：1989-08-04
申请号：JP1702388
申请日：1988-01-29
申请人： HITACHI LTD
发明人： TAKAOKA KAZUHIKO , SUZUKI TAKASHI
IPC分类号： H04B3/10
摘要： PURPOSE:To shorten a convergent time of a equalizer by calculating a receiving quality by means of the square sum of an error signal to be a binary signal at the time of tap coefficient updating due to a data signal, weighting an updated gain when as equivalent residual exists because of the bad receiving quality for a set section from the receipt of the data signal, and controlling the updated gain of an equalizer. CONSTITUTION:When the CD signal of a training signal arrives at the prescribed tap position of an equalizer 2, the same pattern as the sent data in a CD period is outputted from a reference signal generator 5. Here, when line distortion is left at the information data, that is, when the equivalent residual is large, the square sum of the error signal of a received quality calculating circuit 8 becomes larger than a fixed threshold TH. Thus, for the constant section of the information data receipt, the AND of a timer 8 output is obtained by a tap updating/weighting circuit 9, the selector of an equalizer coefficient control circuit 7 selects beta, and the tap updated gain is largely weighted. For this reason, the convergent speed of the equalizer is enhanced, an error does not continue, and the data can be correctly and promptly obtained.

6. 发明专利

JPS63132554A SETTING SYSTEM FOR TELEPHONE LINE MONITOR SOUND VOLUME 失效
公开(公告)号：JPS63132554A
公开(公告)日：1988-06-04
申请号：JP27860686
申请日：1986-11-25
申请人： HITACHI LTD
发明人： SUZUKI TAKASHI , TAKAOKA KAZUHIKO
IPC分类号： H04M1/60
摘要： PURPOSE:To set a telephone line monitor sound volume at a low cost without attaching a variable resistance onto an operating panel, by bringing an operating state of an existing push-button switch to digital coding, and setting and controlling digitally an amplification factor by a telephone line monitoring amplifier. CONSTITUTION:A microcomputer 4 brings an opening/closing state of push- button switches 5, 6 to digital coding so that the push-button switch 5 on an operating panel part 3 increases an amplification factor of an amplifier 1, whenever it is pushed, and the push-button switch executes its reverse operation. Also, to analog switches 10-12, opening/closing control signals 13-15 are outputted. Therefore, resistances 7-9 for determining the amplification factor of the amplifier 1 can be grounded arbitrarily, and the amplification factor of the amplifier 1 can be switched. Accordingly, a telephone line monitor sound volume by a loudspeaker 2 can be set arbitrarily by an operation of the push- button switches 5, 6. Therefore, a variable resistance becomes unnecessary, and a simplification of a structure of the operating panel part, and its low cost can be realized.

7. 发明专利

JPS6292524A MODEN FOR FACSIMILE EQUIPMENT 失效
公开(公告)号：JPS6292524A
公开(公告)日：1987-04-28
申请号：JP23116085
申请日：1985-10-18
申请人： HITACHI LTD
发明人： TAKAOKA KAZUHIKO
IPC分类号： H04B3/06
摘要： PURPOSE:To prevent erroneous adjustment of an equalizer due to noise by applying amplitude limit weighting by a control circuit so as to move a coefficient chip. CONSTITUTION:When an input signal where a synchronizing signal is arranged just before a modulation data is inputted to a demodulator 1, the input signal is subject to synchronization detection, a high frequency portion is eliminated by an LPF 2 and the result is a base band signal, which is inputted to an automatic equalizer 3. The adjustment of the equalizer 3 is started by using an error from a prescribed reference signal. If an erroneous reference signal pattern is generated, the coefficient tap of the equalizer 3 is moved toward the end. An equalizer coefficient control circuit 7 gives a maximum value of weighting to each coefficient tap to move the tap. Thus, the equalization is not initialized and the equalization with degraded equalizing capability such as coming of the main tap to the end tap is prevented in advance.

8. 发明专利

JPS6211170A POWER DETECTION CIRCUIT 失效
公开(公告)号：JPS6211170A
公开(公告)日：1987-01-20
申请号：JP17366086
申请日：1986-07-25
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： ISHIZUKA KOHEI , KITA YASUHIRO , MAEDA SHIGEMICHI , TAKAOKA KAZUHIKO , KOKURYO GARO
IPC分类号： G01R21/06 , H03G3/20
摘要： PURPOSE:To obtain a digitalized power signal of decibel display with good accuracy, by constituting an operation circuit for detecting the input power of a variable gain amplifier on the basis of the output signal of the amplifier and a gain control signal of a floating-point type digital circuit. CONSTITUTION:The analogue signal applied to an input terminal 1 is amplified by a variable gain amplifier capable of varying gain to decibel linear and converted to a digital signal by an A/D converter 7. This signal is applied to the demodulation circuit of a modem from a terminal 2 to be inputted to a square circuit 8 and converted to the signal corresponding to average power from plural sample values by an averaging circuit 9 and said signal is converted to a signal of decibel display by a decibel converter circuit 10. The signal corresponding to average power is displayed by a floating-point system and, on the basis of said result and the gain control signal applied to the amplifier 3, a signal power calculation circuit 11 calculates the power value of the input signal as a digital value.

9. 发明专利

JPS61131681A Carrier wave recovery circuit 失效
标题翻译：载波波形恢复电路
公开(公告)号：JPS61131681A
公开(公告)日：1986-06-19
申请号：JP25185084
申请日：1984-11-30
申请人： Hitachi Ltd
发明人： TAKAOKA KAZUHIKO
IPC分类号： H04N1/40 , H03D1/22 , H03D1/24
摘要： PURPOSE: To obtain the titled circuit having a stabilized phase jitter and short in time of leading-in by providing two kinds of loop filters which generate controlling voltage and using either of them in accordance with an external control.
CONSTITUTION: A converting signal input Si added into a synchronous wave detection circuit 1 is outputted to phase detectors 3a, 3b through an orthogonal distortion compensating filter 2. Each output from the phase detectors 3a, 3b is combined together via LPFs 4a, 4b and then sent to an external control switch 10. The external control switch has a function of switching the said combined output to the first loop filter and the second loop filter 9, and this switching is done by a control signal CONT. For the first loop filter 8, the output which can absorb a frequency offset due to quick synchronous lead-in time is used, and for the second loop filter, the output which can follow up an instantaneous phase change of receiving carrier is used.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过提供两种产生控制电压的环路滤波器，并根据外部控制使用任何一种，获得具有稳定的相位抖动和导通时间短的标称电路。构成：通过正交失真补偿滤波器2将添加到同步波检测电路1中的转换信号输入Si输出到相位检测器3a，3b。来自相位检测器3a，3b的每个输出通过LPF 4a，4b组合在一起，然后发送到外部控制开关10.外部控制开关具有将所述组合输出切换到第一环路滤波器和第二环路滤波器9的功能，并且该切换由控制信号CONT来完成。对于第一环路滤波器8，使用可以吸收由于快速同步引入时间引起的频率偏移的输出，并且对于第二环路滤波器，使用可以跟随接收载波的瞬时相位变化的输出。

10. 发明专利

JPS60190034A Frequency offset distortion initial correction equalizing system 失效
标题翻译：频率偏移初始校正均衡系统
公开(公告)号：JPS60190034A
公开(公告)日：1985-09-27
申请号：JP4541784
申请日：1984-03-12
申请人： Hitachi Ltd
发明人： TAKAOKA KAZUHIKO
IPC分类号： H04B1/76 , H04B3/04 , H04B3/10
CPC分类号： H04B3/04
摘要： PURPOSE:To decrease the locking time and to improve the establishment of locking by using a training signal to correct the initial phase and the frequency offset error of an equalizer with respect to a demodulator incorporated in the automatic equalizer of locking. CONSTITUTION:The timing of an equalizer system is initialized at the reception signal during the period AB, the signal is inputted to a phase error detector 9, where a phase error is detected. The absolute phase is calculated by an absolute phase calculator in the phase error detector 9. The result is inputted to a delay element D and also the phase error is obtained by a circuit subtracting it from the preceding sample value. Then the said phase error is inputted to an integration circuit 10, the initial frequency offset is calculated by a value subjected to the integration of a certain time, it is transferred as the frequency offset information of a carrier generator 8 before the start of a random period to decrease the effect due to the frequency offset during the locking period of the automatic equalizer.
摘要翻译：目的：通过使用训练信号来减少锁定时间并改善建立锁定，以校正均衡器相对于结合在锁定自动均衡器中的解调器的初始相位和频率偏移误差。构成：在周期AB期间，以接收信号初始化均衡器系统的定时，该信号被输入到检测到相位误差的相位误差检测器9。绝对相位由相位误差检测器9中的绝对相位计算器计算。结果被输入到延迟元件D，并且通过从前面的采样值减去它的电路获得相位误差。然后将所述相位误差输入到积分电路10，通过经过一定时间的积分的值来计算初始频率偏移，在随机的开始之前将其作为载波发生器8的频率偏移信息传送以减少在自动均衡器的锁定期间由频率偏移引起的影响。

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