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1. 发明专利

JPS6355785B2 失效
公开(公告)号：JPS6355785B2
公开(公告)日：1988-11-04
申请号：JP3029981
申请日：1981-03-03
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H01L27/04 , H01L21/74 , H01L21/76 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/08

2. 发明专利

JPS57168527A DIGITAL LOGIC CIRCUIT 失效
公开(公告)号：JPS57168527A
公开(公告)日：1982-10-16
申请号：JP5401281
申请日：1981-04-10
申请人： NIPPON ELECTRIC CO , NIPPON ELECTRIC IC MICROCOMPUT
发明人： MORI SUSUMU , NAKAMURA TATSUO
IPC分类号： H03K19/088 , H03K19/003
摘要： PURPOSE:To avoid the breakdown of a digital logic circuit although a short circuit is mistakenly caused between an output terminal and a GND or between the output terminals, by providing a protecting circuit in which the output is set at L only in case the output terminal is forcibly set at L from the outside when the output terminal is set at H. CONSTITUTION:An output 3 is set at H and L when an input 1 is at L and H, respectively. Thus in this case, two inputs of a comparator 40 are not set at L simultaneously. At the same time, an output 41 is set at H to give no effect to the ordinary logic working. In case a terminal 3 is short-circuited to a GND while an input signal of H is applied to the input 1, an ON buffer output circuit 20 is cut off. Accordingly, no overcurrent flows through the circuit 20. On the other hand, if the terminal 3 is short-circuited to the GND while the input signal of L is applied to the input 1, the terminal 3 is forcibly set at L. As a result, the two inputs of the comparator 40 are set at L with the output 41 set at L. Thus the circuit 20 is cut off to break the overcurrent which is about to flow for the time of 10-20ns.

3. 发明专利

JPS56157130A LOGICAL GATE CIRCUIT 失效
公开(公告)号：JPS56157130A
公开(公告)日：1981-12-04
申请号：JP6018180
申请日：1980-05-07
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H03K5/02 , H03K19/013 , H03K19/088
摘要： PURPOSE:To improve the output voltage resistance of a TTL having an off-buffer output circuit, by preventing the voltage applied to an output terminal from flowing backward from the output terminal to a power supply terminal although the said voltage increases higher than the power supply voltage when the output is set at ''1'' level. CONSTITUTION:A Schottky barrier diode (SBD)D7 for base charge lead-out of a transistor Q6 at the post stage of a Darlington off-buffer and a cathode of an SBDD8 for discharge of accumulated charge of a load capacity CL are connected to the collector of a level shift transistor Q1. At the same time, the SBDD9 and D10 are inserted between the collector of Q1 and a resistance R2 as well as between the collector of a transistor Q6 and a resistance R5 respectively so that the cathode of SBD is connected to the collector of each transistor. Thus the SBDD9 and D10 function to prevent the current from flowing backward from an output to a power supply terminal although the voltage applied to an output terminal increases higher than the power supply voltage when the output is set at ''1'' level.

4. 发明专利

JPS57145359A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS57145359A
公开(公告)日：1982-09-08
申请号：JP3029981
申请日：1981-03-03
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H01L27/04 , H01L21/74 , H01L21/76 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/08
摘要： PURPOSE:To excellently prevent the effect of parasitic MOS due to wiring by forming a high impurity-density region below the wiring in a high resistance region when the wiring is provided in the high resistance region of a semiconductor linear integrated circuit wherein a bi-polar transistor is used, through the intermediary of an insulator layer. CONSTITUTION:An N type layer 2 whose density is about 5X10 atom/cm is grown epitaxially on a P type semiconductor auxiliary substrate 1 whose impurity density is about 1X10 atom/cm and the layer 2 is separated in the shape of an island by a P type diffusion region 8 reaching the substrate 1. Next, a P type resistance region 3 whose density is about 1X10 atom/cm is formed diffusely in the island-shaped layer 2, the entire surface is covered with an insulator layer 6, windows are opened in positions at both end parts of the region 3, P type regions 4 and 4' of about 3X10 atom/cm are formed in the region 3, and electrodes 5 and 5' are connected thereto respectively. Thereafter, an Al wiring 7 is provided on the insulator layer 6 surrounded by these electordes 5 and 5'. In this constitution, a P type region 9 whose density is about 3X10 atom/cm is provided beforehand in the region 3 directly under the wiring 7.

5. 发明专利

JPS5552240A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5552240A
公开(公告)日：1980-04-16
申请号：JP12557178
申请日：1978-10-11
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H01L27/082 , H01L21/3205 , H01L21/8222 , H01L23/52 , H01L27/06
摘要： PURPOSE:To provide a semiconductor IC device having excellent input clamping characteristics by forming an npn transistor in a tunnel wiring island region that constitutes part of the input wiring system. CONSTITUTION:An n-type layer 3 is formed in a p-type semiconductor substrate 1 to constitute an island with an isolation layer 4. p-Type impurities are diffused in all areas but an area 31 to form a furth area 5 of the p-type. Further, n-type impurities are diffused in a high concentration to form a third area 61 and area 62. Thereupon an input terminal pad 100 and an input circuit wiring 92 are formed to be connected to the area 61, while the area 62 is connected to a VCC wiring 94 and the substrate 1 to a GND wiring 93, the input wiring intersecting wirings 95 and 96. Thus an npn transistor is formed with the island of layer 3 working as collector, the fourth area 5 as base, and the third area 61 as emitter, so that clamping may take place on the input circuit wiring 92 without being affeted by parasitic resistance.

6. 发明专利

JPS5499580A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5499580A
公开(公告)日：1979-08-06
申请号：JP15885577
申请日：1977-12-27
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H01L27/082 , H01L21/8222 , H01L27/06 , H01L27/08 , H01L29/47 , H01L29/872 , H03K19/013 , H03K19/084
摘要： PURPOSE:To obtain an IC containing the diode which features a small constitution area as well as a low level of the forward voltage by separating the reverse conducting layer grown on the semiconductor substrate into two island-shaped regions and then forming the transistor and the Schottky barrier to one of the two regions and the other respectively. CONSTITUTION:N-type buried region 62 and 62' are formed through diffusion on P-type semiconductor substrate 61, and N-type layer 63 is grown on the entire surface. Then P-type insulation distribution region 64 reaching substrate 61 is formed through diffusion with layer 63 isolated into island region 63 and 63' on region 62 and 62' each. After this, P-type base region 65, N-type emitter region 66 and N-type collector region 67 are provided within region 63 and then covered with insulator film 68 with the opening drilled. And the Schottky barrier forming metal is coated, and Al wiring 71 is attached. In the same way, N-type region 70 and P-type region 72 are provided within the other region 63' along with wiring 71 attached via the Schottky barrier metal. Then the transistor and the Schottky barrier diode are formed within region 63 and 63' respectively.

7. 发明专利

JPH0249574B2 失效
公开(公告)号：JPH0249574B2
公开(公告)日：1990-10-30
申请号：JP3697581
申请日：1981-03-13
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H03K19/088 , H03K19/003 , H03K19/20

8. 发明专利

JPS6318336B2 失效
公开(公告)号：JPS6318336B2
公开(公告)日：1988-04-18
申请号：JP1664179
申请日：1979-02-14
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H01L27/082 , H01L21/8222 , H01L27/06 , H01L27/07 , H01L29/417 , H01L29/47 , H01L29/872

9. 发明专利

JPS6159535B2 失效
公开(公告)号：JPS6159535B2
公开(公告)日：1986-12-17
申请号：JP15885577
申请日：1977-12-27
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H01L27/082 , H01L21/8222 , H01L27/06 , H01L27/08 , H01L29/47 , H01L29/872 , H03K19/013 , H03K19/084

10. 发明专利

JPS6142898B2 失效
公开(公告)号：JPS6142898B2
公开(公告)日：1986-09-24
申请号：JP5676578
申请日：1978-05-12
申请人： NIPPON ELECTRIC CO
发明人： KYOZUKA NOBORU , MORI SUSUMU
IPC分类号： H03K19/0175 , H03K19/082

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