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1. 发明专利

JPH0548563A CHANNEL CHECK TEST METHOD AND CIRCUIT FOR DCME EQUIPMENT 失效
公开(公告)号：JPH0548563A
公开(公告)日：1993-02-26
申请号：JP20427791
申请日：1991-08-14
申请人： NEC CORP , MIYAGI NIPPON DENKI KK
发明人： KATO TADAHARU , SUDAMA TOORU
IPC分类号： H04B17/00 , H04J3/14
摘要： PURPOSE:To discriminate an abnormal result of channel check test for DCME equipment by detecting the start/stop point for sending sine wave tone from positive and negative sign PCM signals of transmission test pattern and establishing test synchronization, and by comparing receiving expectation with the positive and negative PCM signals. CONSTITUTION:Since wave detecting circuit 2 detects 2400Hz sine wave tone from positive and negative PCM signals of INTELSAT standardization system and the detecting result is output to hang-over adding circuit 3. The circuit 3 adds a period of hang-over time when the sine wave signal changes from the presence to the absence and outputs the result to control circuit 9. Likewise, sine wave detecting circuit 4 detects a 1245Hz sine wave signal and outputs the result to circuit 9. Synchronizing circuit 5 compares a PCM signal with the synchronized pattern stored in memory 6 in advance in unit of bit to generate a synchronization control signal and outputs the result to the circuit 9. The circuit 9, based on the input from each circuit, generates a synchronization timing signal and a control signal, and compares the PCM signal with the discriminating pattern of memory 8 at unmatching detecting circuit 7, and to use discriminating circuit 10 to discriminate whether or not the test result is acceptable.

2. 发明专利

JPH04253431A TRANSFORMER MULTIPLEXER 失效
公开(公告)号：JPH04253431A
公开(公告)日：1992-09-09
申请号：JP946491
申请日：1991-01-30
申请人： NEC CORP , MIYAGI NIPPON DENKI KK
发明人： KATO TADAHARU , WAKAO KATSUHIKO
IPC分类号： H04B14/04 , H04J1/00 , H04J3/00
摘要： PURPOSE:To enable economical and efficient transmission by decreasing the number of transmission media (lines) at a transmission line to half of the conventional. CONSTITUTION:An ADPCM conversion part 5 mutually converts two PCM primary group signals, which are the input/output signals of a TDM interface part 4, and an ADPCM primary group signal band-compressing these two PCM primary group signals to one. An ADPCM interface part 6 exchanges the output signal of the ADPCM conversion part 5 and interfaces an ADPCM line 7.

3. 发明专利

JPH0484519A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH0484519A
公开(公告)日：1992-03-17
申请号：JP19891590
申请日：1990-07-26
申请人： NEC CORP , MIYAGI NIPPON DENKI KK
发明人： MORI MASAHIKO , KATO TADAHARU , SHIBAMATA TAKASHI , ENDO KATSUNORI
IPC分类号： H03L7/08
摘要： PURPOSE:To minimize a phase skip caused when a frequency division clock is selected by comparing a frequency division initializing signal outputted from a 1st frequency divider means selected with a frequency division initializing signal outputted from a 2nd frequency divider means not selected and generating a reset control signal when a phase difference is a prescribed value or over. CONSTITUTION:A reset capacitor 5 compares a frequency division initializing signal outputted from a frequency divider 3 selected as a clock of phase comparison object with a frequency division initializing signal outputted from a frequency divider 4 not selected as the clock of phase comparison object. When a phase difference between a frequency division clock selected as a clock of phase comparison object and a frequency division clock not selected as the clock of phase comparison object reaches a prescribed value, the frequency divider 4 outputting the frequency division clock selected as a clock of phase comparison object is reset. Thus, the phase skip caused when a frequency division clock is selected is minimized.

4. 发明专利

JPH02198264A ORDER WIRE EQUIPMENT 失效
公开(公告)号：JPH02198264A
公开(公告)日：1990-08-06
申请号：JP1622389
申请日：1989-01-27
申请人： NEC CORP
发明人： KATO TADAHARU , SENDA FUMIYASU
IPC分类号： H04M11/06
摘要： PURPOSE:To transmit a sound signal and a data signal in a time division system and to attain the transmissions with one channel by sending a low bit rate data signal from a modem interface circuit to a PCM encoding and decoding circuit at the time of no calling. CONSTITUTION:A selecting circuit 13 alternatively selects the output of a tele phone set circuit 11 and the output of a modem interface circuit 14, and outputs the selected output to a PCM encoding and decoding circuit 16, and the selecting operating of the circuit 13 is controlled by the output of a deciding circuit 17. The circuit 17 is the circuit to input the output of the circuit 11 and decide whether a talking circuit is established or not, and the circuit 17 outputs this decided result to the circuit 13. Therefore, when a talking path is established, and a talk is realized, the circuit 13 selects the output of the circuit 11 and outputs the selected output to the circuit 16. On the other hand, at the time of no calling state, the circuit 13 selects the output from the circuit 14 and outputs the selected output to the circuit 16. Consequently, the sound signal and the data signal can be transmitted in the time division system, and both the transmissions can be executed with one channel.

5. 发明专利

JPH0230234A INTERNAL STATE SETTING SYSTEM FOR TRANSCODER 失效
公开(公告)号：JPH0230234A
公开(公告)日：1990-01-31
申请号：JP18105388
申请日：1988-07-19
申请人： NEC CORP
发明人： KATO TADAHARU
IPC分类号： H03M7/36 , H04B14/06
摘要： PURPOSE:To allow the title system to respond to an input signal quickly by deciding the presence of a pulse code modulation signal in the input signal and giving the pulse code modulation signal in the case of the presence and giving a white noise signal in the case of the absence to a code conversion circuit. CONSTITUTION:A signal (PCM signal) inputted from an input terminal 1 is given to an input signal deciding circuit 3 and a selection circuit 4. The input signal deciding circuit 3 decides the presence of the input of a signal having a level, e.g., over a threshold level and gives the result to the selection circuit 4. Upon the receipt of a signal representing the presence of input signal, the selection circuit 4 gives the signal from the input terminal 1 to a code conversion circuit 6, and upon the receipt of a signal representing the absence of input signal on the other hand, the selection circuit 4 selects a white noise signal outputted from a white noise generating circuit 5 and gives the result to the code conversion circuit 6. Although a level of the white noise signal is lower than an average level of the input signal, the level is selected to operate synchronizing tandem control. Thus, quick response to the input signal is attained and the accumulation of code conversion errors in the case of the multi- stage cascade connection is avoided.

6. 发明专利

JPS63316530A LINE CONNECTION INFORMATION TRANSMITTING METHOD FOR 60 CHANNEL ADPCM TRANSCORDER 失效
公开(公告)号：JPS63316530A
公开(公告)日：1988-12-23
申请号：JP15137287
申请日：1987-06-19
申请人： NEC CORP
发明人： KATO TADAHARU
IPC分类号： H04J3/00
摘要： PURPOSE:To eliminate the preparations of a exclusive channel for line connection information by re-writing a current line correspondence table memory to the contents of a spare line correspondence table memory when the changing contents returned from a facing device and the spare line correspondence table memory in its own device are coincident at plural times. CONSTITUTION:At a system 1, when a returned line connection request bit is '01' and the contents of a first register F-REG23 and the contents of a second register S-REG24 are coincident, the contents of a current line correspondence table memory C-MAP 21 are re-written to the contents of a spare line correspondence table memory S-MAP 22. At a system 2, when the contents when they are received by an arrow 30 and the contents when they are received by an arrow 50 are different, the contents of the register F-REG 23 and a line connection changing request bit are set to '10' as shown in an arrow 70 and returned to the system 1. Namely, only when the changing contents transmitted from the system 1 are the same contents as the first register F-REG 23, the contents of a current line memory C-MAP 21 are re-written.

7. 发明专利

JPS6373430A SIGNAL PROCESSOR 失效
公开(公告)号：JPS6373430A
公开(公告)日：1988-04-04
申请号：JP22045886
申请日：1986-09-17
申请人： NEC CORP
发明人： KATO TADAHARU
IPC分类号： G06F12/14 , G06F9/06 , G06F15/78 , G06F21/22 , G06F21/24
摘要： PURPOSE:To secure the same input and output instructions while improving the secrecy of these instructions by applying different decoding methods between an executing mode and an external output mode for instructions ciphered and stored. CONSTITUTION:When an instruction is carried out, a changeover switch 6 is closed at the side of an instruction decoding circuit 8. Then the instruction stored in an instruction storing circuit 4 that is shown by an address inputted through an address input terminal 5 is sent to a 1st decoding circuit 7 having the adverse characteristics to those of a ciphering circuit 2 and decoded there. Then the switch 6 is closed at the side of an output terminal 12 when an instruction is read to outside. The instruction stored in the circuit 4 that is shown by an address inputted through the terminal 5 is sent to a 2nd decoding circuit 10 having a decoding method which is different from that of the circuit 7 and supplied via a cipher key 11 and decoded there.

8. 发明专利

JPS62227240A LINE CORRESPONDING INFORMATION COINCIDENCE SYSTEM FOR ADPCM TRANSCODER 失效
公开(公告)号：JPS62227240A
公开(公告)日：1987-10-06
申请号：JP7194086
申请日：1986-03-29
申请人： NEC CORP
发明人： KATO TADAHARU
IPC分类号： H04Q11/04
摘要： PURPOSE:To make line corresponding information coincident by providing a line corresonding table in the inside of an ADPCM transcoder, inserting its address number in a line sending signaling information in an ADPCM DS1 and transmitting/receiving the number between opposed equipments. CONSTITUTION:Coding/decoding circuits 18,19 input the output of a format conversion circuit 17 corresponding to PCM line interface circuits 15,16, the coder side converts a PCM signal into an ADPCM signal and the decoder side converts the ADPCM signal into the PCM signal respectively. The format conversion circuit 17 applies mutual conversion between the frame constitution of each DSI signal and the frame constitution for internal signal processing between the PCM line interface circuits 15,16 and an ADPCM line interface circuit 20, applies the signal processing including the bundle processing and applies line asignment between a PCM DS1 signal and an ADPCM DSI signal. An address number of a line corresponding list is given to a line sending signaling information and alarm information in the ADPCM DS1 signal at the transmission side. Further, the reception side extracts the number and sends the result to a line corresponding information generating circuit 21.

9. 发明专利

JPS62180627A OPERATING TIME RATE MEASURING CIRCUIT FOR VOICE DETECTOR 失效
公开(公告)号：JPS62180627A
公开(公告)日：1987-08-07
申请号：JP2115386
申请日：1986-02-04
申请人： NEC CORP
发明人： KATO TADAHARU , NISHITANI TAKAO
IPC分类号： H04J3/17
摘要： PURPOSE:To accurately measure the operating time rate of a voice detector by obtaining the number of clock pulses generated within a measuring time and the number of clock pulses generated in the operating time of the voice detector within the measuring time and dividing the latter by the former. CONSTITUTION:The titled circuit consists of the voice detector 1, a clock pulse generating circuit 2, an AND circuit 3, the 1st counter circuit 4, the 2nd counter circuit 5, a control circuit 6 and an operation circuit 7. The operating time of the voice detector is given approximately by a product between the number CNT 1 of clock pulses generated in the operating time of the voice detector and a period Tp of the clock pulse. Supposing the number of clock pulses generated in the measuring time Tm is CNT 2, the measuring time Tm is given as Tm=CNT2XTp. Since the operating time rate of the voice detector is defined as the division of the operation time divided by the measuring time, the operating time rate is obtained by the division of the number of clock pulses generated in the operating time of the voice detector by the number of clock pulses generated in the measuring time.

10. 发明专利

JPS61151700A TIME CONSTANT VARYING TYPE VARIABLE THRESHOLD VOICE DETECTOR 失效
公开(公告)号：JPS61151700A
公开(公告)日：1986-07-10
申请号：JP27731684
申请日：1984-12-26
申请人： NEC CORP
发明人： KATO TADAHARU
IPC分类号： G10L11/00 , G01H3/00 , H04J3/17

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