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1. 发明专利

JPH0415526A VARIABLE INITIAL VALUE TYPE SINGLE TONE DETECTOR 失效
公开(公告)号：JPH0415526A
公开(公告)日：1992-01-20
申请号：JP11937190
申请日：1990-05-09
申请人： NEC CORP , MIYAGI NIPPON DENKI KK
发明人： SATO EIJI , MORI MASAHIKO , NUMATA YOSHIAKI
IPC分类号： G01H17/00
摘要： PURPOSE:To improve the decision rates for deciding a single tone or not even in the case an input signal-to-noise ratio is small by varying an initial value of a coefficient of a filter in accordance with a signal-to-noise ratio derived by a signal power ratio of a sound part and a no-sound part. CONSTITUTION:A secondary adaptive FIR filter 2 is used for detecting a single tone. In the case an inputted digital signal is a sine wave, by using a fact that a secondary filter coefficient a2 is converged to a certain prescribed value, the coefficient a2 of the filter and a threshold are compared by a deciding device 6 and whether the input digital signal is a single tone or not is detected. Also, when the input signal is varied from a no-sound state to a sound state by a signal-to-noise ratio calculating circuit 3, the decision rate for deciding a single tone or not is improved even in the case an input signal-to-noise ratio is small by varying an initial value of the coefficient a2 of the filter in accordance with a signal-to-noise ratio derived by a signal power ratio of a sound part and a no-sound part.

2. 发明专利

JPH0484519A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH0484519A
公开(公告)日：1992-03-17
申请号：JP19891590
申请日：1990-07-26
申请人： NEC CORP , MIYAGI NIPPON DENKI KK
发明人： MORI MASAHIKO , KATO TADAHARU , SHIBAMATA TAKASHI , ENDO KATSUNORI
IPC分类号： H03L7/08
摘要： PURPOSE:To minimize a phase skip caused when a frequency division clock is selected by comparing a frequency division initializing signal outputted from a 1st frequency divider means selected with a frequency division initializing signal outputted from a 2nd frequency divider means not selected and generating a reset control signal when a phase difference is a prescribed value or over. CONSTITUTION:A reset capacitor 5 compares a frequency division initializing signal outputted from a frequency divider 3 selected as a clock of phase comparison object with a frequency division initializing signal outputted from a frequency divider 4 not selected as the clock of phase comparison object. When a phase difference between a frequency division clock selected as a clock of phase comparison object and a frequency division clock not selected as the clock of phase comparison object reaches a prescribed value, the frequency divider 4 outputting the frequency division clock selected as a clock of phase comparison object is reset. Thus, the phase skip caused when a frequency division clock is selected is minimized.

3. 发明专利

JPH0537675A ORDER WIRE EQUIPMENT WITH 2-WIRE FACSIMILE INTERFACE 失效
公开(公告)号：JPH0537675A
公开(公告)日：1993-02-12
申请号：JP21246791
申请日：1991-08-23
申请人： NEC CORP
发明人： MORI MASAHIKO , KATO TADAHARU
IPC分类号： H04M11/00 , H04M9/02 , H04N1/00 , H04N1/32
摘要： PURPOSE:To realize the equipment enabling communication between its own station and other station through the use of a facsimile equipment via an order wire. CONSTITUTION:At least one of input signals received via an order wire 1 is a specific signal including its own station number and an input control signal and the input control signal designates whether a receiver is a handset 6 or a facsimile equipment 15. When the facsimile equipment is designated, the facsimile equipment receives the input signal via the order wire via a branch circuit 2, a line connection switch 5, a handset - facsimile equipment changeover switch 7, a 4/2-wire changeover circuit 8, a 2-wire changeover switch 9 and a facsimile interface 12. When the reception is finished, a control signal detection circuit 3 detects an input end control signal from an input single signal received by the branch circuit, the control circuit 14 outputs an input interruption signal and the line connection switch disconnects the branch circuit from the handset - facsimile equipment changeover switch 7.

4. 发明专利

JPH04100412A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH04100412A
公开(公告)日：1992-04-02
申请号：JP21884590
申请日：1990-08-20
申请人： NEC CORP
发明人： MORI MASAHIKO , NAGAO YOSHIHIRO
IPC分类号： H03L7/08 , H03L7/10
摘要： PURPOSE:To make the catching time of a PLL circuit shorter so that the output clock signal of the circuit can be stabilized by providing a variable time constant type low-pass filter, the time constant of which becomes smaller only when a selecting signal inputted from a clock selecting signal input terminal is inputted, namely, only when the frequency dividing clock outputted from the 1st frequency dividing means is switched. CONSTITUTION:A selector 5 selects one out of the frequency dividing clocks outputted from plural 1st frequency dividers on the basis of a select signal inputted from a clock signal selecting signal input terminal 12. A low-pass filter 7 is of a variable time constant type constituted in such a way that the filter 7 outputs the DC level outputted from a phase comparator 6 to a voltage- controlled oscillator 8 after removing high-frequency components and, at the same time, the time constant of the filter 7 becomes smaller only when the selecting signal inputted from the terminal 12 is inputted, namely, only when the frequency dividing clock outputted from the 1st frequency divider is switched. Therefore, the catching time of this PLL circuit is made shorter even though the phase difference between frequency dividing signals is larger when an input clock signal is discontinued and the clock is switched.

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