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1. 发明专利

JP2003309463A Level shift circuit 审中-公开
标题翻译：水平移位电路
公开(公告)号：JP2003309463A
公开(公告)日：2003-10-31
申请号：JP2002112492
申请日：2002-04-15
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KOBAYASHI TOSHIFUMI
IPC分类号： H03K19/0185 , H03K3/356 , H03K17/10
CPC分类号： H03K17/102 , H03K3/356113
摘要： PROBLEM TO BE SOLVED: To obtain a level shift circuit in which a convertible potential difference is large, a delay time is short and a through current is small.
SOLUTION: A discharging means consists of high voltage correspondence N type transistors MN0101 and MN0102 whose gates are biased to prescribed voltage and low voltage correspondence N type transistors MN0103
- L and MN0104
- L. The prescribed voltage is set to voltage that is in the middle between the threshold voltage of the high voltage correspondence N type transistors MN0101 and MN0102 and the breakdown strength of the low voltage correspondence N type transistors MN0103
- L and MN0104
- L.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题为了获得可转换电位差大的电平移位电路，延迟时间短，通过电流小。解决方案：放电装置包括高电压对应的N型晶体管MN0101和MN0102，其栅极被偏置到规定的电压，低电压对应N型晶体管MN0103 -L和MN0104 < / SB> L。规定的电压被设定为在高电压对应N型晶体管MN0101和MN0102的阈值电压之间的中间的电压和低电压对应N型晶体管MN0103的击穿强度和/ MN0104 - L。版权所有（C）2004，JPO

2. 发明专利

JP2003309462A Level shifting circuit 审中-公开
标题翻译：水平移位电路
公开(公告)号：JP2003309462A
公开(公告)日：2003-10-31
申请号：JP2002112486
申请日：2002-04-15
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KOBAYASHI TOSHIFUMI
IPC分类号： H03K19/0185 , H03K3/356
CPC分类号： H03K3/356165 , H03K3/356113
摘要： PROBLEM TO BE SOLVED: To obtain a level shifting circuit in which a convertible potential difference is large, a delay time is short and a through current is small.
SOLUTION: A charging means is composed of a charge control circuit. In the charge control circuit, when a node N0103 is changed from logic 'H' to logic 'L' due to a change in an input signal IN
- L, a P type transistor MP0104 is set to on to charge a node N0104 into logic 'H', and the P type transistor MP0104 is then returned to an off state. When the node N0104 is changed from logic 'H' to logic 'L' due to a change the input signal IN
- L, the P type transistor MP0103 is set to on to charge the node N0103 into logic 'H' and the P type transistor MP0103 is then returned to an off state.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题为了获得可转换电位差大的电平移动电路，延迟时间短，通电电流小。解决方案：充电装置由充电控制电路组成。在充电控制电路中，由于输入信号IN - L的变化，当节点N0103从逻辑“H”变为逻辑“L”时，P型晶体管MP0104被设置为将节点N0104充电为逻辑“H”，然后P型晶体管MP0104返回到关闭状态。由于输入信号IN - L的改变，当节点N0104从逻辑“H”变为逻辑“L”时，P型晶体管MP0103被设置为接通，以将节点N0103充电为逻辑 'H'和P型晶体管MP0103然后返回到关闭状态。版权所有（C）2004，JPO

3. 发明专利

JPH0352226B2 失效
公开(公告)号：JPH0352226B2
公开(公告)日：1991-08-09
申请号：JP1874784
申请日：1984-02-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： ARIMOTO KAZUTAMI , YAMADA MICHIHIRO , MASUKO KOICHIRO , KOBAYASHI TOSHIFUMI , MYAMOTO HIROSHI , MOROOKA KIICHI
IPC分类号： G11C11/417 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/11

4. 发明专利

JPH03160694A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH03160694A
公开(公告)日：1991-07-10
申请号：JP30052689
申请日：1989-11-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： HAMAMOTO TAKESHI , KOBAYASHI TOSHIFUMI , YAMAGATA NARIHITO , MIHARA MASAAKI
IPC分类号： G11C15/04
摘要： PURPOSE:To reduce operation time and power consumption by writing information in a memory cell where a first control terminal is in an active state at the time of writing and refreshing the memory cell storing same information as first and second bits lines at the time of refreshing. CONSTITUTION:When '1' is stored in a CAM cell, initialization is executed at a cycle CT1, and TrT1 and T2 are turned off. The bit line 6 and the inverse bit line 7 are set to H at CT2 and a coincident line 10 is driven to L. At that time, the potential of the first control terminal 9 is maintained to Vcc-Vth5, Tr 16 is turned on and the potential of a second control terminal 17 comes to a ground potential. A word line 8 is set to H from L at CT3. When data '0' is given to the bit lines 6 and 7, the CAM cell is set in the same state as an initial one, and data 0 is written. When information given to the bit line 6 and the inverse bit line 7 coincide with those stored in a storage node 20 and an inverse storage node 21, information stored in the nodes 20 and 21 are refreshed.

5. 发明专利

JPH0346194A CONTENTS ADDRESS MEMORY CELL 失效
公开(公告)号：JPH0346194A
公开(公告)日：1991-02-27
申请号：JP18322289
申请日：1989-07-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： HAMAMOTO TAKESHI , KOBAYASHI TOSHIFUMI , MIHARA MASAAKI
IPC分类号： G11C15/00 , G11C15/04
摘要： PURPOSE:To detect the number of disaccording contents address memory cells to reduce the power consumption for bit collating operation by comparing stored data and retrieval data with each other to detect the potential level of a coincidence line. CONSTITUTION:When a storage part 70 of a CAM cell 60 is selected by a word line 1, given data is stored in this part 70, and a comparing part 80 compares stored data and retrieval data with each other, and the comparison result is stored in a capacity element 9 in the form of electric charge through a cut-off means 15. The means 15 cuts off a part of the charging/discharging path of the element 9 to prevent stored information electric charge from escaping to lines other than a coincidence line 3. When disaccord information is stored in the element 9, an electric charge migrating means 11 forms a charging/ discharging path between the element 9 and the coincidence line 3. Then, the means 11 migrates a certain quantity of electric charge between the element 9 and the coincidence line 3. Thus, the potential of the coincidence line 3 is changed by a certain potential by the element 9 where disaccord information is stored.

6. 发明专利

JPH02137193A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02137193A
公开(公告)日：1990-05-25
申请号：JP29071788
申请日：1988-11-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： HAMAMOTO TAKESHI , KOBAYASHI TOSHIFUMI , MIHARA MASAAKI
IPC分类号： G11C15/04
摘要： PURPOSE:To attain bit collation operation at a high speed by providing first- fourth switch elements connected to a word line and a bit line, fifth-eighth switch elements, which are connected to the bit line, and an output switch connected to a coincident line. CONSTITUTION:When a word line 8 is activated, a first control circuit 11 accumulates the signal values of first-fourth bit lines 6-1-6-4 to first-fourth capacitors 3-1-3-4. Then, a second control circuit 12 determines the binary condition of activation or inactivation for a control terminal 9 according to the signal values, which are accumulated in the first-fourth capacitors 3-1-3-4, and the signal values of the first-fourth bit liens 6-1-6-4. Then, since the control terminal 9 is activated, an output switch element 8 outputs a coincident signal to a coincident line 10. Thus, the bit collation operation can be executed at the high speed.

7. 发明专利

JPS6310393A OUTPUT CIRCUIT FOR SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6310393A
公开(公告)日：1988-01-16
申请号：JP15650986
申请日：1986-07-01
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOBAYASHI TOSHIFUMI
IPC分类号： G11C11/417 , G11C11/34 , G11C11/409
摘要： PURPOSE:To prevent a through current from flowing, which results in the damage of elements, by providing a pulse generator circuit generating a pulse with a prescribed width when a power source is entered and forcibly causing 1st and 2nd output transistors nonconductive while the pulse is generated. CONSTITUTION:The pulse generator circuit 10 is provided which generates the pulse with the prescribed width when a power source is entered. If times t0-t2 when the voltage of a node N2 is at a level 'H' are set longer than times t0-t1 when a complementary logical signal D and its inversion D are at low levels 'L', signals DH and DL never become the level 'H' simultaneously even if the inverse of an output enable signal DOE is active (level 'L'), and output MOS transistors 4 and 5 become nonconductive simultaneously. Thus the through current never flows to a grounding GND terminal through the output MOS transistors 4 and 5 from the terminal of the power source Vcc. Consequently the current never damages elements.

8. 发明专利

JPS62128092A DYNAMIC RANDOM ACCESS MEMORY 失效
公开(公告)号：JPS62128092A
公开(公告)日：1987-06-10
申请号：JP26842685
申请日：1985-11-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOBAYASHI TOSHIFUMI
IPC分类号： G11C11/407 , G11C11/34 , G11C11/409
摘要： PURPOSE:To attain a stable and highly speedy action by latching a raw address between the starting of a memory action and the completing of a precharging action and executing the action after the latch of a row address after the precharging action is completed. CONSTITUTION:When a started memory action is completed by leading a row address strobing signal the inverse of RAS at time t1, a precharging clock signal, the inverse of phiPR is trailed. When the row address strobing signal, the inverse of RAS is trailed again in time t2 when precharging is not completed, a row address latch clock signal phiRAL comes to be immediately a high level. The precharging of a row address buffer 3 is completed in a very short time and an input address signal ADD is normally latched to the row address buffer 3. When the precharging is completed at time t3, an internal clock signal, the inverse of phiRAS is trailed, a row decoder activating clock signal phiRDE comes to be a high level and a series of the memory action after the row address is decoded is started.

9. 发明专利

JPS6188545A Semiconductor input protection circuit 失效
标题翻译：半导体输入保护电路
公开(公告)号：JPS6188545A
公开(公告)日：1986-05-06
申请号：JP21000984
申请日：1984-10-05
申请人： Mitsubishi Electric Corp
发明人： ARIMOTO KAZUTAMI , MIYAMOTO HIROSHI , KOBAYASHI TOSHIFUMI , YAMADA MICHIHIRO
IPC分类号： H01L23/62 , H01L27/02 , H01L23/56
CPC分类号： H01L27/0288
摘要： PURPOSE:To obtain input protection circuit having good heat dissipation efficiency by inserting a conductor layer through an interlayer insulating film at the lower side of protection resistance on the occasion of providing both input terminal and ground terminal on a semiconductor substrate and connecting a MOS transistor connecting in series protection resistance between such terminals. CONSTITUTION:A ground terminal 3 and an input terminal 4 are provided on a semiconductor substrate 6 and when a MOS transistor 2 is connected between these terminals, a protection resistance 1 consisting of a polycrystalline Si is connected in series in order to protect the transistor 2 from a surge input. In this structure, the protection resistance 1 is embedded into PSG film 8 provided on a substrate 6 and in this case a wide conductive layer 5 made of polycrystalline Si having good heat radiating efficiency is provided in parallel to a protection resistance 1 is also embedded in parallel through the interlayer insulating film 9 between the protection resistance 1 and film 8. Thereby, the heat generated can be radiated efficiently and the protection resistance 1 does not generate melting.
摘要翻译：目的：通过在半导体衬底上提供输入端子和接地端子的情况下，通过在保护电阻下侧的层间绝缘膜插入导体层来获得具有良好散热效率的输入保护电路，并连接MOS晶体管连接在这种端子之间串联保护电阻。构成：在半导体基板6上设置接地端子3和输入端子4，在MOS晶体管2连接在这些端子之间时，由多晶硅构成的保护电阻1串联连接，以保护晶体管2 从浪涌输入。在这种结构中，保护电阻1嵌入到设置在基板6上的PSG膜8中，并且在这种情况下，与保护电阻1并联地设置具有良好散热效率的多晶Si制成的宽导电层5也嵌入通过保护电阻1和膜8之间的层间绝缘膜9并联。从而，可以有效地辐射所产生的热量，并且保护电阻1不产生熔化。

10. 发明专利

JPS60236192A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS60236192A
公开(公告)日：1985-11-22
申请号：JP9488684
申请日：1984-05-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMADA MICHIHIRO , MASUKO KOUICHIROU , KOBAYASHI TOSHIFUMI , MIYAMOTO HIROSHI , ARIMOTO KAZUTAMI , MOROOKA KIICHI
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE:To prevent a rise time delay of an edge of a word line by providing a word line driver auxiliary circuit on an edge further away from the word line with respect to a word line driver circuit. CONSTITUTION:A word line driver auxiliary circuit charged only at a rise of a line 5 formed by an MOS transistor 10 connected to a power source voltage VCC, etc., is provided on an edge further away from a word line driver circuit of a word line 5. Thanks to said circuit, a word line edge part can rise quickly although a resistance exists on the word line, and the occurrence of a rise delay can be prevented.

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