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1. 发明专利

JP2007043622A Clock generating apparatus 审中-公开
标题翻译：钟表生成装置
公开(公告)号：JP2007043622A
公开(公告)日：2007-02-15
申请号：JP2005228180
申请日：2005-08-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , KISHIMOTO YOSHIHIRO , KUBO HIRONORI , SEKIGUCHI YUJI
IPC分类号： H03K5/05 , G06F1/08 , H03K5/00
摘要： PROBLEM TO BE SOLVED: To solve the problem that jitter or duty deterioration of N-mutiplied (N is a positive integer) clock may occur by varying a delay value of a delay circuit because of process variation in the prior art where the N-multiplied clock is generated by exclusively ORing N clocks delayed for a 1/2N term by the delay circuit. SOLUTION: According to the present invention, a signal delayed for a 1/2N (N is a positive integer) term in advance is input from the outside, so that delay of a delay circuit is not varied by variation of semiconductor manufacturing processes. Therefore, jitter or duty deterioration can be reduced for an N-multiplied clock generated by exclusive OR, so that a high-precision N-multiplied clock can be generated. Furthermore, the N-multiplied clock is output outside a semiconductor integrated circuit, frequency dispersion or duty deterioration is computed and an input timing and a duty of the input signal are adjusted, thereby supplying a high-precision N-multiplied clock. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题为了解决由于现有技术中的工艺变化而改变延迟电路的延迟值，可能会发生N倍频（N为正整数）时钟的抖动或占空比恶化的问题，其中通过对延迟电路延迟1 / 2N项的N个时钟进行异或运算，产生N倍乘时钟。解决方案：根据本发明，从外部输入预先延迟1 / 2N（N为正整数）项的信号，使得延迟电路的延迟不会因半导体制造的变化而变化流程。因此，通过异或产生的N倍时钟可以降低抖动或占空比恶化，从而可以产生高精度的N倍时钟。此外，将N倍时钟输出到半导体集成电路外部，计算频率色散或占空比劣化，并且调节输入定时和输入信号的占空比，从而提供高精度的N倍时钟。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006189916A Timing adjustment method and device 有权
标题翻译：时序调整方法和设备
公开(公告)号：JP2006189916A
公开(公告)日：2006-07-20
申请号：JP2004381496
申请日：2004-12-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KISHIMOTO YOSHIHIRO , MIKI YOICHIRO , SEKIGUCHI YUJI
IPC分类号： G06F12/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： PROBLEM TO BE SOLVED: To adjust the timing of latching an external strobe signal and external data synchronized with the signal, with a system clock. SOLUTION: A strobe signal s100a from a memory 100 is delayed through delay circuits 1031 to 103n of a strobe delay selection part 103 to a plurality of delayed strobe signals. A strobe latch part 106 generates check data at the reception timing of each delayed strobe signal, and a system latch part 107 latches the check data latched in the strobe latch part 106, with a system clock s200. According to a comparison and determination in an expected value comparison part 108 and a delay determination part 109, an optimum strobe signal delayed optimally in the strobe delay selection part 103 is selected. Data s100b from the memory 100 is then delayed through delay circuits 1041 to 104n of a data delay selection part 104 to a plurality of delayed data, from which optimum data delayed optimally is selected according to the comparison and determination in the expected value comparison part 108 and delay determination part 109. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：使用系统时钟调整锁定外部选通信号和与信号同步的外部数据的时序。解决方案：来自存储器100的选通信号s100a通过选通延迟选择部分103的延迟电路1031至103n被延迟到多个延迟的选通信号。选通锁存部分106在每个延迟的选通信号的接收定时产生检查数据，并且系统锁存部分107用系统时钟s200锁存锁存在选通锁存器部分106中的校验数据。根据期望值比较部分108和延迟确定部分109的比较和确定，选择在选通延迟选择部分103中最佳延迟的最佳选通信号。然后，来自存储器100的数据s100b通过数据延迟选择部分104的延迟电路1041至104n被延迟到多个延迟数据，根据预期值比较部分108中的比较和确定，最佳数据被延迟最优延迟确定部分109.（C）2006，JPO＆NCIPI

3. 发明专利

JP2007148914A Latch timing adjustment device and adjustment method therefor 审中-公开
标题翻译：锁定时间调整装置及其调整方法
公开(公告)号：JP2007148914A
公开(公告)日：2007-06-14
申请号：JP2005344196
申请日：2005-11-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SEKIGUCHI YUJI , MIKI YOICHIRO , KISHIMOTO YOSHIHIRO , TOMIOKA SHINICHI
IPC分类号： G06F12/00
摘要： PROBLEM TO BE SOLVED: To attain a latch timing adjustment device capable of adjusting difference between rising edge timing and trailing edge timing of data input from a memory.
SOLUTION: The latch timing adjustment device has: a data delay part 14A which generates delay data D1 more delayed by an instructed amount than that of input data S10; a data delay part 14B which generates delay data D2 having a delay amount different from that of the delay data D1; an edge adjustment part 15 which performs a logic operation to the delay data D1, D2 to generate delay data D3; a latch circuit 16 which latches the delay data D3 at prescribed timing; a comparison circuit 17 which compares the latched data S16a with an expectation value; a determination part 18 which determines delay amounts which should be set in the data delay parts 14A, 14B based on comparison results and delay control parts 19A, 19B which output delay control signals S19a, S19b for instructing the delay amounts of the data delay parts 14A, 14B.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：获得能够调整从存储器输入的数据的上升沿定时和后沿定时之间的差异的锁存定时调整装置。锁存定时调整装置具有：数据延迟部14A，其生成比输入数据S10更延迟了指示量的延迟数据D1; 产生具有与延迟数据D1不同的延迟量的延迟数据D2的数据延迟部分14B; 边缘调整部15，对延迟数据D1，D2进行逻辑运算，生成延迟数据D3; 锁存电路16，其以规定的定时锁存延迟数据D3; 将锁存数据S16a与期望值进行比较的比较电路17; 确定部分18，其基于比较结果确定在数据延迟部分14A，14B中应该设置的延迟量;以及延迟控制部分19A，19B，延迟控制部分19A，19B输出用于指示数据延迟部分14A的延迟量的延迟控制信号S19a，，14B。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2004185608A Device for adjusting latch timing of data 有权
公开(公告)号：JP2004185608A
公开(公告)日：2004-07-02
申请号：JP2003386499
申请日：2003-11-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SEKIGUCHI YUJI , MIKI YOICHIRO
IPC分类号： G06F12/00
摘要： PROBLEM TO BE SOLVED: To automatically adjust latch timing for data, while reducing the number of latch circuits to be provided.
SOLUTION: A read controller 104 reads out first check data, which are written in a memory 100, from a check data storage part 102 and then outputs a latch pulse signal s104c to a delay selection part 105. The selection part 105a outputs a delayed pulse signal, with the latch pulse signal s104c being delayed at a leading delay circuit 1051, to a latch circuit 106. The latch circuit 106 latches the check data from the memory 100, when it receives the delayed pulse signal. Subsequently, next data is read out from the memory 100, and the selection part 105a outputs a delayed pulse signal, which is delayed at a delay circuit 1052 located in the following stage, to the latch circuit 106.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2003215204A SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT AND METHOD FOR TESTING THE SAME 审中-公开
公开(公告)号：JP2003215204A
公开(公告)日：2003-07-30
申请号：JP2002010728
申请日：2002-01-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SEKIGUCHI YUJI
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, and a circuit and a method for testing the semiconductor integrated circuit, which suppress an increasing ratio of a dull section in a waveform at the frequency of an output signal made faster in accordance with speed-up operation of semiconductor integrated circuits, and can carry out a stable test of the semiconductor integrated circuits. SOLUTION: The semiconductor integrated circuit 100 under test includes a strobe generating circuit 105 and a flip-flop 107 which switches from an output of an inner circuit 106 to an output generated by dividing the output of the inner circuit 106, or vice versa in accordance with an output of the strobe generating circuit 105 and outputs the output. In the test mode, the strobe generating circuit 105 selects and outputs an output signal generated by dividing the output signal from the inner circuit 106. COPYRIGHT: (C)2003,JPO

6. 发明专利

JP2001222251A VIDEO SIGNAL CONVERTER 失效
公开(公告)号：JP2001222251A
公开(公告)日：2001-08-17
申请号：JP2000157907
申请日：2000-05-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MUTO YASUAKI , NIWA AKIO , AZUMA TAKUMA , WAKAHARA TOSHIO , SEKIGUCHI YUJI , MORITA TOMOKO
IPC分类号： G09G3/20 , G09G5/00 , G09G5/36 , G09G5/391 , H04N5/46 , H04N7/01
摘要： PROBLEM TO BE SOLVED: To provide a video signal converter that vertical frequency conversion, IP conversion, scanning line conversion and horizontal pixel conversion are systematically conducted with no waste as a one system using video signals having a small amount of data stored in one place and the video signals are converted into video signals suitable for a display device that conducts matrix display. SOLUTION: Field video data to be required for IP conversion and scanning line conversion are stored in a field memory section 7. Vertical frequency conversion is conducted by a memory control processing section 2 using the data stored in the section 7. The IP conversion is conducted by an IP conversion processing section 3, the scanning line conversion is performed by a scanning line conversion processing section 4 and the horizontal pixel conversion is done by a horizontal pixel conversion processing section 5.

7. 发明专利

JP2001167570A LINE MEMORY DEVICE 失效
公开(公告)号：JP2001167570A
公开(公告)日：2001-06-22
申请号：JP34982199
申请日：1999-12-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SEKIGUCHI YUJI
IPC分类号： G11C7/00 , H04N5/907
摘要： PROBLEM TO BE SOLVED: To store even the serial data of the final cycle that are smaller than the number of bits of parallel data with no loss and then read the serial data into and out of a line memory which stores the inputted serial data after converting them into the parallel data. SOLUTION: The line memory device 100 includes a line memory macro 101 which uses serial/parallel conversion, a shift register 111 which has its capacity equal to the bit width of the data to be converted into the parallel data, a selector 109 and a control block 110 which controls the register 111 and selector 109. In such a constitution, it is possible to store all digital signals S102 in the memory 100 and then to read them out with no loss by storing the data (which cannot be stored in the macro 101) of the final cycle whose signals S102 are smaller than the number of bits of serial/parallel conversion into the register 111.

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