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1. 发明专利

JP2007281111A Solid-state electrolytic capacitor and solid-state electrolytic capacitor-incorporated substrate, and method of manufacturing these 审中-公开
标题翻译：固态电解电容器和固态电解电容器并入基板及其制造方法
公开(公告)号：JP2007281111A
公开(公告)日：2007-10-25
申请号：JP2006103776
申请日：2006-04-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ASAHI TOSHIYUKI , HIMORI GOJI , ISHITOMI HIROYUKI , SUGAYA YASUHIRO , SASAKI TOMOE
IPC分类号： H01G9/14 , H01G9/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To achieve a low ESL characteristic by preventing the concentration of a current and reducing a self-inductance component by cancellation of magnetic fields appearing in a direction of the current inside a wide through-hole electrode in form of a long hole. SOLUTION: The solid-state electrolytic capacitor comprises: a negative pole 104 arranged nearly in parallel to a positive pole 101; an electrode 105 formed on an insulation layer 103; and through-hole electrodes 106 which pass through the insulation layer 103 and the positive pole 101 to electrically connect between the electrode 105 and the positive pole 101 and/or pass through the insulation layer 103 and the negative pole 104 to electrically connect between the electrode 105 and the negative pole 104. At least one of the through-hole electrodes 106 has a shape of a long hole. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了通过防止电流的集中和通过消除在宽通孔电极内的电流方向出现的磁场而减小自感分量来实现低ESL特性，形式为一个长洞解决方案：固态电解电容器包括：几乎平行于正极101布置的负极104; 形成在绝缘层103上的电极105; 以及通过绝缘层103和正极101的通孔电极106，以电连接电极105和正极101和/或穿过绝缘层103和负极104，以电连接电极 105和负极104.至少一个通孔电极106具有长孔的形状。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008130870A Circuit substrate, and its manufacturing method 审中-公开
标题翻译：电路基板及其制造方法
公开(公告)号：JP2008130870A
公开(公告)日：2008-06-05
申请号：JP2006315218
申请日：2006-11-22
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SASAKI TOMOE , ASAHI TOSHIYUKI , SUGAYA YASUHIRO
IPC分类号： H05K3/46 , H05K1/16
摘要： PROBLEM TO BE SOLVED: To provide a circuit substrate which can form a capacitor on an optional location/shape of a circuit substrate with an aluminum foil as a wiring layer, and to provide its manufacturing method. SOLUTION: The circuit substrate includes an insulating substrate 1, a plurality of wiring layers which are formed on the insulating substrate 1 and at least one layer is to be an aluminum foil 4, a solid aluminum electrolytic capacitor 5 which is formed on a part of the wiring layer 3 composed of the aluminum foil, and a via 6 which is formed on the insulating substrate 1 and electrically connects between the solid aluminum electrolytic capacitor 5 and the wiring layer and/or the wiring layers each other. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种电路基板，其可以在铝箔作为布线层的电路基板的任选位置/形状上形成电容器，并提供其制造方法。解决方案：电路基板包括绝缘基板1，形成在绝缘基板1上的多个布线层和至少一层为铝箔4，固体铝电解电容器5形成在由铝箔构成的布线层3的一部分和形成在绝缘基板1上并且将实心铝电解电容器5与布线层和/或布线层电连接的通孔6。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2008078530A Circuit board and manufacturing method thereof 审中-公开
标题翻译：电路板及其制造方法
公开(公告)号：JP2008078530A
公开(公告)日：2008-04-03
申请号：JP2006258543
申请日：2006-09-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ASAHI TOSHIYUKI , SASAKI TOMOE , SUGAYA YASUHIRO
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a circuit board from which high wiring accuracy can be obtained by adjusting a dimensional error cased during the production of a wiring board by selecting a curing temperature of an adhesion layer using the thermal expansion difference between a binding member and a wiring board.
SOLUTION: The circuit board comprises an electrical insulating layer 101, a wiring board 105 having a wiring pattern 102 formed on a main surface of at least one side of the electrical insulating layer, a binding member 104 having a thermal expansion coefficient different from that of the wiring board, and an adhesion layer 103 adhering the wiring board and the binding member, wherein the curing temperature of the adhesion layer is made lower than the glass transition temperature of the wiring board. The accurate circuit board can be obtained from this configuration that enables highly accurate adjustment of the wiring accuracy using the thermal expansion difference between the electrical insulating surface and the binding member.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种电路板，通过使用以下的热膨胀差来选择粘合层的固化温度，通过调整布线板制造期间的尺寸误差来获得高布线精度装订件和接线板。解决方案：电路板包括电绝缘层101，具有形成在电绝缘层的至少一侧的主表面上的布线图案102的布线板105，具有热膨胀系数不同的粘合构件104 与布线基板的固化温度相比，使粘接层的固化温度低于布线基板的玻璃化转变温度。可以从该配置获得精确的电路板，其能够使用电绝缘表面和装订构件之间的热膨胀差来高精度地调整布线精度。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007335487A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007335487A
公开(公告)日：2007-12-27
申请号：JP2006163137
申请日：2006-06-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SASAKI TOMOE , ASAHI TOSHIYUKI
IPC分类号： H01L23/32 , H01L23/12 , H05K1/11 , H05K1/18 , H05K3/32 , H05K3/46
CPC分类号： H01L2224/16225 , H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can establish electrical connection stable to thermal stress and wherein semiconductor elements can be arranged in three-dimensional manner.
SOLUTION: The semiconductor device is provided with: a semiconductor element 7 provided with a plurality of external terminals 8; a wiring substrate 4 formed of a first electrically insulating base 1 and a wiring pattern 10 that is provided with a connection pad 2 formed in the first electrically insulating base 1; and a second electrically insulating base 5 to adhere the semiconductor element 7 to the wiring substrate 4. In this case, the external terminal 8 and the connection pad 2 are electrically connected with each other through a via 6 formed in the second electrically insulating base 5.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以建立对热应力稳定的电连接的半导体器件，并且其中半导体元件可以以三维方式布置。解决方案：半导体器件设置有：设置有多个外部端子8的半导体元件7; 由第一电绝缘基体1和布线图案10形成的布线基板4，布线图案10设置有形成在第一电绝缘基底1中的连接焊盘2; 以及第二电绝缘底座5，以将半导体元件7粘附到布线基板4.在这种情况下，外部端子8和连接焊盘2通过形成在第二电绝缘基底5中的通孔6彼此电连接（C）2008，JPO＆INPIT

5. 发明专利

JP2007221117A Substrate incorporated with components, and its manufacturing method 审中-公开
标题翻译：与组件合并的基板及其制造方法
公开(公告)号：JP2007221117A
公开(公告)日：2007-08-30
申请号：JP2007011005
申请日：2007-01-22
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SASAKI TOMOE , ASAHI TOSHIYUKI , SUGAYA YASUHIRO
IPC分类号： H05K3/46 , G01R1/073 , H01L21/66 , H01L23/12
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a substrate incorporated with components inexpensively with high reliability, which obtains high-density packaging with high substrate dimension accuracy, and to provide its manufacturing method. SOLUTION: The substrate incorporated with components is characterized by comprising: a first electrically insulating substrate 1; a plurality of circuit boards 4 comprising a wiring pattern 2 formed on both sides of the first electrically insulating substrate 1 and arranged on the same plane; a circuit component 6 mounted on the circuit board 4; a correcting material 8 with a thermal expansion coefficient lower than that of the circuit board 4; and a second electrically insulating substrate 7 having the circuit component 6 embedded to bond a plurality of circuit boards 4 that are arranged on the same plane with the correcting material 8. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供以高可靠性廉价地组装成分的基板，其获得具有高基板尺寸精度的高密度封装并提供其制造方法。＆lt; P＆gt;解决方案：结合有部件的基板的特征在于包括：第一电绝缘基板1; 多个电路板4，包括形成在第一电绝缘基板1的两侧并布置在同一平面上的布线图案2; 安装在电路板4上的电路部件6; 具有低于电路板4的热膨胀系数的校正材料8; 和第二电绝缘基板7，其具有嵌入的电路部件6以与校正材料8配置在同一平面上的多个电路板4接合。（C）2007，JPO＆INPIT

6. 发明专利

JP2005150447A Wiring board and its manufacturing method 审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2005150447A
公开(公告)日：2005-06-09
申请号：JP2003386646
申请日：2003-11-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIGASHIYA HIDEKI , SUGAWA TOSHIO , SASAKI TOMOE
IPC分类号： H05K3/40 , H05K3/20 , H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board of an all-layer IVH structure at a high density in which, even when a wiring is made finer, a sufficiently wiring adhesion strength can be ensured; and to provide its manufacturing method. SOLUTION: The wiring board comprises electrically insulating substrates 1, 7 of one layer or more and a wiring pattern formed on at least one face of the electrically insulating substrates 1, 7. A side face of the wiring pattern is subjected to an adhesion process which differs from an adhesion process which is performed on front and rear surfaces of the wiring pattern, and the adhesion process which differs from that on the front and rear surfaces of the wiring pattern is performed on an end face of the wiring pattern, thereby further enhancing the adhesion strength of the wiring. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供高密度的全层IVH结构的多层布线板，其中即使布线更细，可以确保足够的布线粘合强度; 并提供其制造方法。解决方案：布线板包括一层或多层的电绝缘基板1,7和形成在电绝缘基板1,7的至少一个面上的布线图案。布线图案的侧面经受在布线图案的端面上进行与布线图案的前表面和背面的粘附处理不同的附着处理和与布线图案的表面和背面不同的粘合处理，从而进一步提高布线的粘合强度。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2007194516A Compound wiring board and its manufacturing method, mounted shape of electronic component, and manufacturing method 审中-公开
标题翻译：复合导线板及其制造方法，电子元器件的安装形状及制造方法
公开(公告)号：JP2007194516A
公开(公告)日：2007-08-02
申请号：JP2006013376
申请日：2006-01-23
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SASAKI TOMOE , SUGAYA YASUHIRO , ASAHI TOSHIYUKI
IPC分类号： H05K3/46
CPC分类号： H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/15153 , H01L2924/19105 , H01L2924/00012 , H01L2224/48227
摘要： PROBLEM TO BE SOLVED: To provide a compound wiring board which is flexibly adaptive to design alterations by easily making a substrate multi-layered at an arbitrary position, and to provide a compound wiring board having a cavity structure where circuit components can be arranged in three dimensions. SOLUTION: The compound wiring board comprises a first wiring board which has a first electric insulating base material and a wiring pattern formed on the first electric insulating base material; a second wiring board which has a second electric insulating base material and a wiring pattern formed on the second electric insulating base material, and in a part of which a cavity is formed in at least a portion of it; and a third electric insulating base material which has a conductor unit electrically connecting the wiring pattern of the first wiring board and the wiring pattern of the second wiring board, while the first wiring board and the second wiring board are bonded together along the thickness, and in a part of which a cavity is formed in at least a portion of it. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过在任意位置容易地使基板多层化而灵活地适应设计变更的复合布线板，并且提供具有空腔结构的复合布线板，其中电路部件可以是三维排列。解决方案：复合布线板包括第一布线板，其具有第一电绝缘基材和形成在第一电绝缘基材上的布线图案; 第二布线板，其具有形成在所述第二电绝缘基材上的第二电绝缘基材和布线图案，并且其一部分中的空腔形成在所述第二布线基板的至少一部分中; 以及第三电绝缘基材，其具有导电单元，所述导体单元将所述第一布线板的布线图案与所述第二布线板的布线图案电连接，同时沿着所述厚度将所述第一布线板和所述第二布线板接合在一起;以及在其一部分中，在其一部分中形成空腔。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006294886A Packaging method of semiconductor element 审中-公开
标题翻译：半导体元件的封装方法
公开(公告)号：JP2006294886A
公开(公告)日：2006-10-26
申请号：JP2005114142
申请日：2005-04-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SASAKI TOMOE , HIGASHIYA HIDEKI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16 , H01L2224/16235 , H01L2224/83192 , H01L2924/01046 , H01L2924/01079
摘要： PROBLEM TO BE SOLVED: To realize packaging of high electrical reliability. SOLUTION: In the packaging method of a semiconductor element, an electrical insulating base material 101 is at first formed in an upper surface of a resin sheet 102, a cover film 110 is then formed in an upper surface of the electrical insulating base material 101, a hole reaching the resin sheet 102 is formed from an upper surface of the cover film 110, the hole is then charged with a conductive paste 104, the cover film 110 is thereafter removed, a connection pad 106 is formed in a circuit substrate 105, the circuit substrate 105 and the electrical insulating base material 101 are joined so that the connection pad 106 and an opening part of the hole come into contact with each other, and the semiconductor element 107 is pressed to the circuit substrate 105 from the resin sheet 102 side so that an electrode of the semiconductor element 107 is fitted inside the hole. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：实现高电气可靠性的封装。解决方案：在半导体元件的封装方法中，首先在树脂片102的上表面形成电绝缘基材101，然后在电绝缘基底的上表面形成覆盖膜110 材料101，从覆盖膜110的上表面形成到达树脂片102的孔，然后用导电膏104填充孔，然后除去覆盖膜110，在电路中形成连接焊盘106 基板105，电路基板105和电绝缘基材101接合，使得连接焊盘106和孔的开口部彼此接触，并且半导体元件107从电路基板105 树脂片102侧，使得半导体元件107的电极嵌入孔内。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006041145A Method for mounting pressing device, and semiconductor bare chip 审中-公开
标题翻译：安装压力装置的方法和半导体切片
公开(公告)号：JP2006041145A
公开(公告)日：2006-02-09
申请号：JP2004218165
申请日：2004-07-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAGI YUJI , KASHIWAGI TAKAFUMI , NIIMI HIDEKI , SASAKI TOMOE
IPC分类号： H01L21/60
CPC分类号： H01L24/83 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/83192 , H01L2224/83194 , H01L2924/01079 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress the extrusion of thermosetting resin paste to the minimum by solving the problem, wherein since thermosetting resin paste is centralized in the neighborhood of the center of the outer periphery of a semiconductor bare chip and extruded by almost 1.0 mm in semiconductor bare chip mounting by the thermosetting resin paste using a conventional pressing device, peripheral components cannot be mounted inside this, and the miniaturization of module components is hindered. SOLUTION: In this pressing device, a pressing tool 1 whose section positioned in the neighborhood of the center of the outer periphery of a semiconductor bare chip 2 is turned into a low-temperature section 1b is used so that, when heat and a pressure are added to the semiconductor bare chip 2, the increase in the temperature can be reduced in the neighborhood of the center of the outer periphery of the semiconductor chip 2, and the viscosity of resin paste 3 can be made higher than a section to be heated. Thus, flow can be suppressed, and extrusion can be reduced, and peripheral components more adjacent to the semiconductor chip 2 than a conventional manner can be mounted, and to further miniaturize module components. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了通过解决问题来抑制热固性树脂浆料的挤出最小化，其中由于热固性树脂浆料集中在半导体裸芯片的外周的中心附近并被几乎挤出通过使用常规的按压装置的热固性树脂浆料安装的半导体裸芯片为1.0mm，不能在其内部安装周边部件，并且妨碍了模块部件的小型化。解决方案：在该按压装置中，使用将位于半导体裸芯片2的外周的中心附近的部分的压制工具1转换为低温部1b，使得当加热和向半导体裸芯片2添加压力，可以在半导体芯片2的外周的中心附近降低温度的升高，并且可以使树脂浆料3的粘度高于加热。因此，可以抑制流动，并且可以降低挤出，并且可以安装比常规方式更靠近半导体芯片2的外围部件，并且进一步使模块部件小型化。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2006351819A BOARD WITH BUILT-IN COMPONENT 审中-公开
公开(公告)号：JP2006351819A
公开(公告)日：2006-12-28
申请号：JP2005175937
申请日：2005-06-16
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SASAKI TOMOE , ASAHI TOSHIYUKI , SUGAYA YASUHIRO , KATSUMATA MASAAKI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a board with built-in components in which, using existing circuits and circuit boards, reliable parts are incorporated at a low cost to realize high-density mounting, and a thermal expansion coefficient is properly controlled by jointing to a correction materia of which appropriate thermal expansion coefficient can be selected. SOLUTION: The board with built-in components comprises a first electric insulating substrate 1; a circuit board 4 consisting of a wiring pattern 2 formed on both surfaces of the first electric insulating substrate 1; a circuit component 6 which is mounted on the circuit board 4, a correction material 8 whose thermal expansion coefficient is lower than the circuit board 4; and a second electric insulating substrate 7 of which, incorporating the circuit component 6, the circuit board 4 is jointed to the correction material 8 whose thermal expansion coefficient is lower. COPYRIGHT: (C)2007,JPO&INPIT

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