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1. 发明专利

JP2004199727A Reproduced signal processor 有权
公开(公告)号：JP2004199727A
公开(公告)日：2004-07-15
申请号：JP2002363615
申请日：2002-12-16
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OKAMOTO YOSHIFUMI , KAWABE AKIRA
IPC分类号： G11B5/035 , G11B20/10 , G11B20/14 , H04B3/06
CPC分类号： G11B20/10101 , G11B5/035 , G11B20/10009 , G11B20/10046 , G11B20/10425 , G11B2020/1863
摘要： PROBLEM TO BE SOLVED: To enhance recording density by making it possible to perform reproduction of data or the like recorded on an optical disk with a high degree of accuracy.
SOLUTION: A digital filter 107 is set between an A/D converter 106, an adaptive equalization filter 109 and a PLL circuit 111. An analog filter 103 mainly has only a low pass function. A controller section 112 determines a tap number which minimizes a jitter value detected by the PLL circuit 111 by setting a variety of tap coefficients in the digital filter 107 during a learning period before reproduction. The determined tap coefficient is set in the digital filter 107 at reproducing, an optimum pre-equalizing is performed, and the recorded data are highly precisely reproduced.
COPYRIGHT: (C)2004,JPO&NCIPI

2. 发明专利

JP2003298424A Signal processor and d/a converter 审中-公开
标题翻译：信号处理器和转换器
公开(公告)号：JP2003298424A
公开(公告)日：2003-10-17
申请号：JP2002104269
申请日：2002-04-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OKAMOTO YOSHIFUMI
IPC分类号： H03L7/08 , H03L7/087 , H03L7/113 , H03M1/68 , H03M1/74 , H03M1/82 , H03M3/00
CPC分类号： H03M7/3002 , G11B20/10037 , H03L7/087 , H03L7/093 , H03M1/68 , H03M3/50
摘要： PROBLEM TO BE SOLVED: To realize a D/A converter in an analog/digital mixed loop within a smaller circuit area while maintaining a high resolution without lowering the resolution. SOLUTION: A bit modulating part 15 modulates a digital control signal DT11 of (m) bits outputted from a digital part into an intermediate digital signal DT21 of (n) bits (n COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：在较小的电路区域内实现模/数混合回路中的D / A转换器，同时保持高分辨率而不降低分辨率。解调器：位调制部分15将从数字部分输出的（m）位的数字控制信号DT11调制为（n）位（n

3. 发明专利

JP2006180428A Phase-locked loop circuit 有权
标题翻译：相位锁定环路
公开(公告)号：JP2006180428A
公开(公告)日：2006-07-06
申请号：JP2004374265
申请日：2004-12-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MICHIMASA SHIRO , MORIE TAKASHI , OKAMOTO YOSHIFUMI , SOKAWA KAZUAKI , YAMADA SUKETSUGU
IPC分类号： H03L7/093
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： PROBLEM TO BE SOLVED: To optimally control loop bandwidth of a phase-locked loop circuit. SOLUTION: The phase-locked loop circuit comprises a gain setting circuit 60 for setting a gain of a voltage controlled oscillator 40, and a time constant setting circuit 70 for setting a time constant determined from a magnitude of a current of a charge pump circuit 20 and a capacity value of a loop filter 30. The loop bandwidth of the phase-locked loop circuit is set to a desired value by setting the gain to a predetermined value by the gain setting circuit 60 and setting the time constant to a predetermined value by the time constant setting circuit 70. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：最佳地控制锁相环电路的环路带宽。解决方案：锁相环电路包括用于设定压控振荡器40的增益的增益设定电路60，以及用于设定由电荷电流的大小确定的时间常数的时间常数设定电路70 泵电路20和环路滤波器30的容量值。通过由增益设定电路60将增益设定为预定值，将锁相环电路的环路带宽设定为期望值，并将时间常数设定为时间常数设定电路70的预定值。（C）2006，JPO＆NCIPI

4. 发明专利

JP2004185669A Wobble signal processing device 有权
公开(公告)号：JP2004185669A
公开(公告)日：2004-07-02
申请号：JP2002348374
申请日：2002-11-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MORI HIROKI , OKAMOTO YOSHIFUMI , OGURA YOICHI
IPC分类号： G11B20/14 , G11B7/005 , G11B7/007 , G11B20/10 , H03M7/14
CPC分类号： G11B7/0053
摘要： PROBLEM TO BE SOLVED: To provide a wobble signal processing device for solving the problem that usual processing of analog system is easily influenced by uneven processes in a semiconductor process, reduces the scale of a circuit, saves electric power and improves the quality of the processing signals.
SOLUTION: A means for decreasing an area and decreasing electric power consumption realized by making the detecting of errors possible by digitally processing a part conventionally processed by an analog system or introducing a PRML circuit is proposed. The proposition is a means which improves the detection of a signal inputted to the wobble signal processing device.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2002367287A Automatic gain control circuit 有权
标题翻译：自动增益控制电路
公开(公告)号：JP2002367287A
公开(公告)日：2002-12-20
申请号：JP2001174590
申请日：2001-06-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KAWABE AKIRA , OKAMOTO YOSHIFUMI
IPC分类号： H04N5/91 , G11B20/10 , H03G3/20 , H03G3/30 , H03M1/18
CPC分类号： H03G3/3084
摘要： PROBLEM TO BE SOLVED: To provide an automatic gain control circuit in which a stable output of a variable gain control circuit is obtained.
SOLUTION: A gain control signal VC in accordance with difference between a peak value of a reproduction signal DS and the upper limit value or the lowest limit value of a dynamic range of an A/D converter 5 is given to a variable gain amplifier 3 in a state in which a PLL circuit 6 is not locked. In a state in which the PLL circuit 6 is locked, a gain control signal VC in accordance with difference between the reproduction signal DS and reference values d1-d5 corresponding to levels LV1-LV5 to which the reproduction signal DS belongs is given to the variable gain amplifier 3. The variable gain amplifier 3 amplifies a reproduction signal AS2 with gain in accordance with the gain control signal VC.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种自动增益控制电路，其中获得可变增益控制电路的稳定输出。解决方案：根据再现信号DS的峰值与A / D转换器5的动态范围的上限值或下限值之间的差异的增益控制信号VC被提供给可变增益放大器3 PLL电路6未被锁定的状态。在PLL电路6被锁定的状态下，根据再现信号DS与对应于再现信号DS所属的电平LV1-LV5的参考值d1-d5之间的差异的增益控制信号VC被赋予该变量增益放大器3.可变增益放大器3根据增益控制信号VC以增益放大再现信号AS2。

6. 发明专利

JP2003283384A Equalizer and regenerated signal processor 有权
标题翻译：均衡器和再生信号处理器
公开(公告)号：JP2003283384A
公开(公告)日：2003-10-03
申请号：JP2002086120
申请日：2002-03-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAHIRA HIROYUKI , NAGANO KOICHI , OKAMOTO YOSHIFUMI , YAMAMOTO AKIRA
IPC分类号： G11B20/10 , H04B3/06 , H04L25/03
CPC分类号： H04L25/03038 , H04L2025/03477 , H04L2025/03585 , H04L2025/03617
摘要： PROBLEM TO BE SOLVED: To provide an equalizer which can accurately compensate nonlinearity of an input signal which is caused by an asymmetry phenomenon or the like when a disk is manufactured.
SOLUTION: Two tap coefficients c
ip , c
in are prepared in coefficient multipliers 102-i. A comparator 103 compares the value of a center tap signal x
3 , a reference signal, with a threshold 108, and produces a selection signal SS on the basis of comparison results. On the basis of the selection signal SS, the coefficient multipliers 102-i select either one of the tap coefficients c
ip , c
in as a selection tap signal c
i , and multiplies x
i by c
i . As a result, the tap coefficients of the whole equalizer can be adaptively switched over, according to the value of center tap signal x
3 , the reference signal, so that the accurate compensation to the nonlinearity of an input signal is enabled.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种均衡器，其可以精确地补偿当制造盘时由不对称现象等引起的输入信号的非线性。解决方案：在系数乘法器102-i中准备在中的两个抽头系数c ip ，c 。比较器103将中心抽头信号x SB 3的值与参考信号与阈值108进行比较，并且基于比较结果产生选择信号SS。在选择信号SS的基础上，系数乘法器102-i选择中的抽头系数c ip ，c 中的任一个作为选择抽头信号c i ，并将x i 乘以c i 。结果，可以根据中心抽头信号x 3 的参考信号自适应地切换整个均衡器的抽头系数，使得对输入的非线性的精确补偿信号被使能。版权所有（C）2004，JPO

7. 发明专利

JP2005032414A REPRODUCING SIGNAL PROCESSOR AND OPTICAL DISK DEVICE 审中-公开
公开(公告)号：JP2005032414A
公开(公告)日：2005-02-03
申请号：JP2004181436
申请日：2004-06-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OGURA YOICHI , TAKAHASHI TOSHIHIKO , AIDA KAZUTOSHI , OKAMOTO YOSHIFUMI
IPC分类号： G11B20/14 , G11B20/10 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To improve the synchronous pull-in speed of an PLL for generating a sampling clock to be used for the A/D conversion of a reproducing signal from an optical disk medium and to simultaneously obtain a binary output based on a PRML signal processing system and a binary output based on the other system. SOLUTION: In the case of generating a sampling clock of an analog/digital (A/D) converter 5 for digitizing a reproducing signal from the optical disk medium 1, an over sampling clock 12 generated by the PLL 100 is used. The zero crossing position information and reference information of a reproduced digital signal 6 obtained by A/D conversion by the over sampling clock 12 are converted into information synchronized with a channel bit clock 14 by an operation period conversion means 9 and the converted information is supplied to a PRML signal processing means 17 and a level discriminating binarizing means 18. COPYRIGHT: (C)2005,JPO&NCIPI

8. 发明专利

JP2002025202A CLOCK EXTRACTING CIRCUIT 失效
公开(公告)号：JP2002025202A
公开(公告)日：2002-01-25
申请号：JP2000205304
申请日：2000-07-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAMOTO TAKASHI , OKAMOTO YOSHIFUMI
IPC分类号： H04N5/91 , G11B20/14 , H03L7/107 , H04L7/033 , H04L27/00 , H04L27/06
摘要： PROBLEM TO BE SOLVED: To speedingly stabilize the operation of a clock extracting system used in reproducing or the like of data recorded on a recording medium. SOLUTION: A phase error dectecting section 30 is provided in addition to a phase error detecting section 20 which is a feedback element to extract clock signals by a conventional digital type feedback control. The section 30 is a feed forward element to detect phase errors based on the output of a comparator provided internal to an analog digital converter 15. The section 30 adaptively controls and adjusts the loop gain of the section 20.

9. 发明专利

JPH10125008A SYNCHRONOUS CLOCK GENERATING DEVICE 失效
公开(公告)号：JPH10125008A
公开(公告)日：1998-05-15
申请号：JP27316696
申请日：1996-10-16
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HAMADA TADAO , YAMAMOTO TAKASHI , NAGANO KOICHI , OKAMOTO YOSHIFUMI
IPC分类号： G11B20/14
摘要： PROBLEM TO BE SOLVED: To prevent time required to lock PLL from becoming long while enabling a conventional PLL system to be utilized even when a PR method is changed, by newly providing a preamble data detector corresponding to a waveform equalizer. SOLUTION: A preamble signal detecting block 9 detects a preamble data from an output of an A/D convertor 5 to output a control signal to a waveform equalizer 6, in order to switch characteristics of a transmission line. Then, upon detecting the preamble data generated by a preamble signal generator 2, the waveform equalizer 6 outputs the output data of the A/D converter 5 in a convolutional manner which is based on a scheme employed in the preamble signal generator 2. In the case for normal data, the waveform equalizer 6 outputs, in accordance with the control signal, the output data of the A/D converter 5 in a convolutional manner which is based on a PR method. Thus, even when the PR method is changed, a conventional preamble pattern can be employed upon locking PLL.

10. 发明专利

JPH1023082A VITERBI DECODING CIRCUIT 失效
公开(公告)号：JPH1023082A
公开(公告)日：1998-01-23
申请号：JP17890196
申请日：1996-07-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAGANO KOICHI , YAMAMOTO TAKASHI , HAMADA TADAO , OKAMOTO YOSHIFUMI
IPC分类号： G11B20/18 , H03M13/23 , H04L25/08 , H04L25/497 , H03M13/12
摘要： PROBLEM TO BE SOLVED: To change the filter characteristic of a waveform equalizer and the characteristic of a compensating circuit by adding redundant data to the output of the waveform equalizer which convolutes and encodes present data and past data, through the use of the compensating circuit. SOLUTION: A viterbi decoding circuit is provided with the waveform equalizer 1, a viterbi decoder 2, the compensating circuit 3, a transmission path 4, a modulating circuit 6, a demodulating circuit 7 and a precoder 9. Then, data are added to output data (ak ) of the modulating circuit 6, through the use of the compensating circuit 3. When the additional bit is given to the output data (ak ) of the modulating circuit 6 such as this, a path is selected and latest data are decoded. The additional bit is given to the output data of the demodulating circuit 6 in the case of two patterns, so that latest decoding data of the viterbi decoder 2 are decided. Thus, the positive decoding of viterbi decoding is enabled by the compensating circuit 3.

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