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1. 发明专利

JP2008016557A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008016557A
公开(公告)日：2008-01-24
申请号：JP2006184696
申请日：2006-07-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NASU TORU
IPC分类号： H01L21/8246 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having the stacked memory cell structure which can prevent the generation of the contact faultiness caused by a heat treatment performed under an oxygen atmosphere. SOLUTION: The semiconductor device has: first and second conductive layers (103a), (103b) present on a substrate (101); a first insulating film (104); first and second plugs (106a), (106b); a first metal film (107a) connected electrically with the first plug (106a); a second metal film (107b) connected electrically with the second plug (106b); a metal oxide film (109) having an opening (109a) of subjecting the second metal film (107b) to an exposure; and a third metal film (110) formed on the metal oxide film (109). The second metal film (107b) is connected with the third metal film (110) via the opening (109a), and the second metal film (107b) and the metal oxide film (109) exist in series on the second plug (106b). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有堆叠式存储单元结构的半导体器件，其可以防止在氧气氛下进行的热处理引起的接触故障的产生。解决方案：半导体器件具有：存在于基板（101）上的第一和第二导电层（103a），（103b）; 第一绝缘膜（104）; 第一和第二插头（106a），（106b）; 与第一插头（106a）电连接的第一金属膜（107a）; 与第二插头（106b）电连接的第二金属膜（107b）; 具有对第二金属膜（107b）进行曝光的开口（109a）的金属氧化物膜（109）和形成在金属氧化物膜（109）上的第三金属膜（110）。第二金属膜（107b）经由开口（109a）与第三金属膜（110）连接，第二金属膜（107b）和金属氧化物膜（109）串联在第二插塞（106b）上，。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006261579A Capacitive element, method of manufacturing the same and semiconductor memory device comprising the same 审中-公开
标题翻译：电容元件及其制造方法和包含其的半导体存储器件
公开(公告)号：JP2006261579A
公开(公告)日：2006-09-28
申请号：JP2005080197
申请日：2005-03-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NASU TORU , HAYASHI SHINICHIRO , MIKAWA TAKUMI
IPC分类号： H01L27/105 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To suppress increase in a leak current, deterioration of pressure resistance, film fatigue and occurrence of imprinting regarding a ferroelectric film while suppressing increase in the resistance of a lower electrode, in a capacitive element comprising the lower electrode constituted of a platinum group metal oxide film and a capacitive film constituted of the ferroelectric film.
SOLUTION: A capacitive element 115 comprises a lower electrode 112, a capacitive film 113 formed on the lower electrode 112, and an upper electrode 114 formed on the capacitive film 113. The lower electrode 112 includes a crystal phase constituted of a first oxide, and an amorphous phase constituted of a second oxide. The first oxide contains at least one kind of platinum group metal oxide, and free energy of formation of the second oxide is smaller than free energy of formation of the first oxide.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在包括下电极的电容元件中，抑制泄漏电流的增加，耐压性的恶化，耐压性降低，并且在抑制下电极的电阻的增加的同时，在铁电体膜上产生压印由铂族金属氧化物膜和由铁电体膜构成的电容膜构成。解决方案：电容元件115包括下电极112，形成在下电极112上的电容膜113和形成在电容膜113上的上电极114.下电极112包括由第一氧化物和由第二氧化物构成的非晶相。第一氧化物含有至少一种铂族金属氧化物，第二氧化物的形成自由能小于形成第一氧化物的自由能。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005079538A Ferroelectric film, ferroelectric capacitive element, and manufacturing method of them 审中-公开
标题翻译：电磁膜，电磁电容元件及其制造方法
公开(公告)号：JP2005079538A
公开(公告)日：2005-03-24
申请号：JP2003311724
申请日：2003-09-03
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAYASHI SHINICHIRO , NASU TORU
IPC分类号： C23C28/00 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric, capable of preventing a polarization property of a ferroelectric capacitor to a crystal grain size difference of the ferroelectric from deteriorating and which will not produce deterioration, even if a capacitor size is reduced accompanying microfabrication of a device, a capacitive element using the ferroelectric, and to provide a method of manufacturing the ferroelectric and the capacitive element.
SOLUTION: The ferroelectric capacitive element is provided with an insulating film 13a formed on a substrate 1, a lower electrode 5 embedded in the insulating film 13a so that at least a part of a front surface of the lower electrode 5 is exposed, a ferroelectric film 12 formed so as to extend over the insulating film 13a and the lower electrode 5, and an upper electrode 7 formed on the ferroelectric film 12. A crystal grain size of the ferroelectric film 12 is formed almost uniformly on the insulating film 13a contacting with the ferroelectric and on the lower electrode 5.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使随着微细加工而使电容器尺寸减小，也能够防止铁电体电容器的极化特性与铁电体的晶粒尺寸差异劣化并且不会产生劣化的铁电体的器件，使用铁电体的电容元件，以及提供制造铁电体和电容元件的方法。解决方案：铁电电容元件设置有形成在基板1上的绝缘膜13a，嵌入在绝缘膜13a中的下电极5，使得下电极5的前表面的至少一部分露出，形成为在绝缘膜13a和下电极5上方延伸的铁电体膜12和形成在强电介质膜12上的上电极7.铁电膜12的晶粒尺寸几乎均匀地形成在绝缘膜13a上与铁电体和下电极5接触。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005033022A Ferroelectric film forming method 有权
标题翻译：电磁膜形成方法
公开(公告)号：JP2005033022A
公开(公告)日：2005-02-03
申请号：JP2003271229
申请日：2003-07-07
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NASU TORU
IPC分类号： C23C16/40 , H01L21/316 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To form a ferroelectric film in a bismuth layer structure by using low temperature crystallization in the MOCVD process.
SOLUTION: The method for forming a ferroelectric film in a bismuth layer structure has a step of introducing at least a first raw material gas comprising a first organic metal compound described by the formula: A[Bi(OR
1 )(OR
2 )(OR
3 )(OR
4 )]
2 , a second raw material gas comprising a second organic metal compound described by the formula: B(OR
5 )(OR
6 )(OR
7 )(OR
8 )(OR
9 ), and an oxidizing gas, into a treatment chamber for film formation by metal-organic chemical vapor deposition.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过在MOCVD工艺中使用低温结晶来形成铋层结构中的铁电体膜。解决方案：在铋层结构中形成铁电体膜的方法具有引入至少第一原料气体的步骤，所述第一原料气体包含由下式所示的第一有机金属化合物：A [Bi（OR / SP>）（OR 2 ）（OR 3 ）（OR 4 ）] SB <2> 包含由下列通式表示的第二有机金属化合物的物质气体：（OR SP 5）（OR SP 6）（OR SP 6） SP> 8 ）（OR 9 ）和氧化气体进入用金属有机化学气相沉积成膜的处理室。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2008147491A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008147491A
公开(公告)日：2008-06-26
申请号：JP2006334350
申请日：2006-12-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NASU TORU
IPC分类号： H01L21/8242 , H01L21/3205 , H01L21/8246 , H01L23/52 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent increased resistance at an electrode of a capacitance element and disconnection.
SOLUTION: In a semiconductor memory device 100 wherein a plurality of capacitance elements 112 are formed on a semiconductor substrate 101, each of the plurality of capacitance elements 112 has a bottom electrode 109, a metal oxide film 110 formed on the bottom electrode 109, and a top electrode 111 formed on the metal oxide film 110. One of the bottom electrode 109 and the top electrode 111 is a common electrode formed to function as an wiring to be connected among many capacitance elements 112. The common electrode is composed of a mixture of platinum group metal and platinum group metal oxide, and has at least a conductive path made of platinum group metal along the wiring direction in the common electrode.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止电容元件的电极上的电阻增加和断开。解决方案：在半导体存储器件100中，多个电容元件112形成在半导体衬底101上，多个电容元件112中的每一个具有底部电极109，形成在底部电极上的金属氧化物膜110 109和形成在金属氧化物膜110上的顶部电极111.底部电极109和顶部电极111中的一个是形成为在多个电容元件112之间连接的布线的公共电极。公共电极组成的铂族金属和铂族金属氧化物的混合物，并且在公共电极中至少具有沿着布线方向的铂族金属的导电路径。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007184440A Ferroelectric capacitor and manufacturing method thereof 审中-公开
标题翻译：电力电容器及其制造方法
公开(公告)号：JP2007184440A
公开(公告)日：2007-07-19
申请号：JP2006002094
申请日：2006-01-10
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAYASHI SHINICHIRO , NASU TORU
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01G4/085 , H01G4/1254 , H01G4/33 , H01L28/55 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor that has improved polarization inversion characteristics and can be operated stably.
SOLUTION: The ferroelectric capacitor comprises a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. The film thickness of the ferroelectric film is 120 nm or smaller, and the polarization inversion time of the ferroelectric film is 200 ns or smaller.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有改善的极化反转特性并且可以稳定地操作的铁电电容器。
解决方案：铁电电容器包括下电极，形成在下电极上的铁电膜和形成在铁电体膜上的上电极。铁电体膜的膜厚为120nm以下，强电介质膜的极化反转时间为200ns以下。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2007005639A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007005639A
公开(公告)日：2007-01-11
申请号：JP2005185314
申请日：2005-06-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKAWA TAKUMI , NASU TORU
IPC分类号： H01L21/8246 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L28/55 , H01L27/11502 , H01L27/11507 , H01L28/65 , H01L28/91
摘要： PROBLEM TO BE SOLVED: To provide a dielectric memory having a stereoscopically stacked structure wherein the wiring delay caused by its upper electrode of a cell plate is prevented and its high integration and its high-speed operation are made possible, without depending on the materials used in its dielectric film and its capacitor upper electrode.
SOLUTION: A semiconductor device has a plurality of capacitor elements each of which comprises an insulating film (14) having a first recess (15a) formed on a semiconductor substrate (10), a capacitor lower electrode (16) having a second recess (15b) formed on the walls and the bottom of the first recess (15a), a capacitor insulating film (17) comprising a dielectric film and having a third recess (15c) formed on the walls and the bottom of the second recess (15b), and a capacitor upper electrode (18A) formed on the walls and the bottom of the third recess (15c). Further, the semiconductor device has a low-resistance conductive layer (19A) having a lower resistance than the one of the capacitor upper electrode (18A) which covers at least a portion of the capacitor upper electrodes (18A) constituting the plurality of capacitor elements, and is so formed as to ride the plurality of capacitor elements.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决方案：为了提供一种具有立体层叠结构的电介质存储器，其中防止了由其电池板的上电极引起的布线延迟并且其高集成度和高速操作成为可能，而不依赖于其电介质膜中使用的材料及其电容器上电极。解决方案：半导体器件具有多个电容器元件，每个电容器元件包括具有形成在半导体衬底（10）上的第一凹部（15a）的绝缘膜（14），具有第二绝缘膜的电容器下电极（16）形成在第一凹部（15a）的壁和底部的凹部（15b），包括电介质膜的电容器绝缘膜（17），并且具有形成在第一凹部的壁和底部的第三凹部（15c） 15b）和形成在第三凹部（15c）的壁和底部上的电容器上电极（18A）。此外，半导体器件具有比覆盖构成多个电容器元件的电容器上电极（18A）的至少一部分的电容器上电极（18A）的电阻低的低电阻导电层（19A）并且被形成为骑乘多个电容器元件。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006148025A Capacitance insulation film and manufacturing method thereof, capacitive element and manufacturing method thereof, and semiconductor memory and manufacturing method thereof 有权
标题翻译：电容绝缘膜及其制造方法，电容元件及其制造方法及其半导体存储器及其制造方法
公开(公告)号：JP2006148025A
公开(公告)日：2006-06-08
申请号：JP2004339472
申请日：2004-11-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAYASHI SHINICHIRO , NASU TORU
IPC分类号： H01L21/316 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11502 , C23C16/40 , C23C16/56 , H01L21/31691 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To provide a capacitance insulation film having a sufficient polarization characteristic even when the capacitive element is miniaturized.
SOLUTION: The capacitance insulation film 21 comprises a ferroelectric film formed on a semiconductor substrate 11, and the ferroelectric film includes an element acting like a crystal core whereby the crystal is grown such that the crystal orientation is a random orientation.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使当电容元件小型化时，也提供具有足够的极化特性的电容绝缘膜。电容绝缘膜21包括形成在半导体基板11上的铁电体膜，并且铁电体膜包括作为晶体核的元件，由此晶体生长使得晶体取向为随机取向。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005223361A Semiconductor storage device and its manufacturing method 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2005223361A
公开(公告)日：2005-08-18
申请号：JP2005115889
申请日：2005-04-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NASU TORU , NAGANO YOSHIHISA
IPC分类号： C23C14/34 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To surely improve the barrier property of an iridium oxide film contained in the lower electrode of a capacitance element as an oxygen barrier film.
SOLUTION: An interlayer insulating film 14 is formed on a semiconductor substrate 10 to cover a field-effect transistor, and a contact plug 15 is formed in the insulating film 14 so that the plug 15 may be connected to the drain region 12. The lower electrode 16 of the capacitance element is formed on the insulating film 14 so that the electrode 16 may be connected to the plug 15, and the electrode 16 is constituted of a first-conductivity barrier film 16a, a second-conductivity barrier film (oxygen barrier film) 16b consisting of the iridium oxide film, and a metallic film 16c. The mean crystal grain diameter of the granular crystals constituting the second-conductivity barrier film 16b is adjusted to at most 1/2 of the thickness of the film 16.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了确保提高包含在作为氧阻隔膜的电容元件的下电极中的氧化铱膜的阻挡性。解决方案：在半导体衬底10上形成层间绝缘膜14以覆盖场效应晶体管，并且在绝缘膜14中形成接触插塞15，使得插塞15可以连接到漏区12 电容元件的下电极16形成在绝缘膜14上，使得电极16可以连接到插塞15，电极16由第一导电阻挡膜16a，第二导电阻挡膜（氧阻隔膜）16b和金属膜16c。构成第二导电阻挡膜16b的粒状晶体的平均晶粒直径被调整为膜16厚度的至多1/2。（C）2005，JPO＆NCIPI

10. 发明专利

JP2005183576A Manufacturing method for ferroelectric thin film and for capacitive element 有权
标题翻译：用于电磁薄膜和电容元件的制造方法
公开(公告)号：JP2005183576A
公开(公告)日：2005-07-07
申请号：JP2003420680
申请日：2003-12-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NASU TORU , HAYASHI SHINICHIRO
IPC分类号： C23C16/40 , H01L21/316 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To suppress a c-axis orientation and reduce a heat budget necessary for crystallization in manufacturing a ferroelectric thin film having a bismuth layer structure.
SOLUTION: A manufacturing method for the ferroelectric thin film is provided. The method includes a process of forming a sedimentary film containing at least Bi, A, and B on a board, and a process of crystallizing the sedimentary film by a heat treatment to form the ferroelectric thin film represented by the chemical formula: Bi
2 A
m-1 B
m O
3m+3 (where m stands for 2, 3, 4, 5, or 6; A stands for any one of metals having 1, 2, or 3 valences or a metal made by combining those metals; and B stands for any one of metals having 4, 5, or 6 valences or a metal made by combining those metals.) The process of forming the sedimentary film includes a process of changing the composition ratio of Bi in the sedimentary film in a direction of film thickness, so that the composition ratio of Bi becomes maximum near the center of the sedimentary film in the direction of film thickness.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：制造具有铋层结构的铁电薄膜时，抑制c轴取向并降低结晶所需的热量预算。解决方案：提供了一种用于铁电薄膜的制造方法。该方法包括在板上形成至少含有Bi，A和B的沉积膜的方法，以及通过热处理使沉积膜结晶化的工序，形成由以下化学式表示的铁电薄膜：Bi 2 A m-1 O 3m + 3 （其中m代表2,3,4,5，或6; A代表任何一种具有1,2或3价的金属或通过组合这些金属制成的金属; B代表任何一种具有4,5或6价金属或通过组合这些金属制成的金属金属）形成沉积膜的过程包括在膜厚方向上改变沉积膜中Bi的组成比的方法，使得Bi的组成比在沉积膜的中心附近在方向的膜厚度。版权所有（C）2005，JPO＆NCIPI

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