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1. 发明专利

JP2008091602A Method for manufacturing resistance-variable memory element material 审中-公开
标题翻译：制造电阻可变存储元件材料的方法
公开(公告)号：JP2008091602A
公开(公告)日：2008-04-17
申请号：JP2006270382
申请日：2006-10-02
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KANZAWA YOSHIHIKO , TAKAGI TAKESHI , MIKAWA TAKUMI , ARITA KOJI , KAWASHIMA YOSHIO , GI SHIKIYO
IPC分类号： H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide a method for preventing change in resistance value of iron oxide by unintended heat treatment in manufacturing a resistance-variable memory element using iron oxide.
SOLUTION: The method relates to manufacturing a memory element composed of a first electrode, a second electrode and a variable resistance thin film connected between the first electrode and the second electrode and includes a process for forming a first iron oxide film as a variable resistance thin film and a process for heat treating the first iron oxide film in an atmosphere including no oxygen to change it into a second iron oxide film. The first iron oxide film can include maghemite (γ-Fe
2 O
3 ), hematite (α-Fe
2 O
3 ), or magnetite (Fe
3 O
4 ) and maghemite (γ-Fe
2 O
3 ). Maghemite changes into hematite through heat treatment in an atmosphere including no oxygen. The temperature of heat treatment is preferably 300°C or more.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过在制造使用氧化铁的电阻变化存储元件时通过非预期热处理来防止氧化铁电阻值变化的方法。解决方案：该方法涉及制造由第一电极，第二电极和连接在第一电极和第二电极之间的可变电阻薄膜组成的存储元件，包括形成第一氧化铁膜作为可变电阻薄膜和在不含氧的气氛中对第一氧化铁膜进行热处理以将其变成第二氧化铁膜的方法。第一氧化铁膜可以包括磁赤铁矿（γ-Fe 2 3 ），赤铁矿（α-Fe 2 / SB>）或磁铁矿（Fe 3 SB 3 O 3）和磁赤铁矿（γ-Fe SB 2 O 3 / SB 3））。通过在不含氧的气氛中进行热处理，金刚石变为赤铁矿。热处理的温度优选为300℃以上。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008091601A Nonvolatile memory element, and its manufacturing method 审中-公开
标题翻译：非易失性存储元件及其制造方法
公开(公告)号：JP2008091601A
公开(公告)日：2008-04-17
申请号：JP2006270381
申请日：2006-10-02
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKAWA TAKUMI , TAKAGI TAKESHI
IPC分类号： H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide an element structure of a nonvolatile memory element which is suitable for miniaturization and speed-up, because it is difficult to miniaturize and speed up a nonvolatile memory element composed of a capacitor and a transistor. SOLUTION: A memory section is composed of variable resistance films 23 which are formed on lower electrodes 25 and striped second lines 21 which are formed perpendicularly to first lines 22 on the variable resistance films 23, cover the top including sides of the variable resistance films 23 and are extended toward the outside. The top of the variable resistance films 23 on the lower electrodes 25 are electrically connected with the top of connection electrodes 27 through the second lines 21 and electrodes are lead out downward from them. In this way, element isolation in the nonvolatile memory element 20 whose variable resistance films 23 are used as memory materials can be reliably performed by isolating the variable resistance films 23 and the connection electrodes 27 so that they may not contact with one another directly. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供适合于小型化和加速的非易失性存储元件的元件结构，因为难以使由电容器和晶体管构成的非易失性存储元件小型化并加快速度。解决方案：存储部分由形成在可变电阻膜23上的与第一线22垂直形成的下电极25和条纹第二线21上的可变电阻膜23组成，覆盖包含可变电阻膜23的顶部的顶部。电阻膜23并且向外延伸。下电极25上的可变电阻膜23的顶部通过第二线21与连接电极27的顶部电连接，并且电极从它们向下引出。以这种方式，通过将可变电阻膜23和连接电极27隔离使得它们可以不直接彼此接触，可以可靠地执行其可变电阻膜23用作存储材料的非易失性存储元件20中的元件隔离。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007281211A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007281211A
公开(公告)日：2007-10-25
申请号：JP2006105945
申请日：2006-04-07
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKAWA TAKUMI , ODAKAWA AKIHIRO , KAWASHIMA YOSHIO
IPC分类号： H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can increase a manufacturing yield and a quality by preventing contamination of a magnetic material caused when a thin film including the magnetic material is formed on a semiconductor substrate and in particular, by removing contaminants produced on the rear surface of the semiconductor substrate.
SOLUTION: The method includes, at least, a step of forming a thin film including a magnetic material on a main surface 10a of a semiconductor substrate 10, and a rear-surface contaminant removing step of removing contaminants 12 made of the magnetic material present on a rear surface 10b of the semiconductor substrate 10 opposed to the main surface 10a by magnetic attraction after the thin film forming step. In the rear-surface contaminant removing step, for example, a tape 22 having at least an abrasive of a magnetically attracting property applied thereonto is contacted with the rear surface of the substrate 10 to be polished, and at the same time, the contaminants are removed by being magnetically attracted to the tape surface.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，该半导体器件可以通过防止当在半导体衬底上形成包括磁性材料的薄膜时引起的磁性材料的污染而提高制造成品率和质量，并且特别地，通过去除在半导体衬底的后表面上产生的杂质。解决方案：该方法至少包括在半导体衬底10的主表面10a上形成包括磁性材料的薄膜的步骤，以及去除由磁性材料制成的污染物12的背面污染物去除步骤存在于通过薄膜形成步骤之后通过磁吸引而与主表面10a相对的半导体衬底10的后表面10b上的材料。在后表面污染物去除步骤中，例如，至少具有施加在其上的吸引磁性的研磨剂的带22与待抛光的基板10的后表面接触，同时污染物通过磁吸引到带表面去除。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2006210634A Semiconductor memory device and its manufacturing method 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2006210634A
公开(公告)日：2006-08-10
申请号：JP2005020542
申请日：2005-01-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTA KATSUYUKI , MIKAWA TAKUMI
IPC分类号： H01L27/105 , H01L21/768 , H01L21/8246
CPC分类号： H01L27/11507 , H01L21/76834 , H01L21/76877 , H01L27/11502 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To realize a capacitor structure which is prevented from deteriorating in characteristics due to a seam formed on a plug that is electrically connected to a lower electrode in the capacitor which uses a capacitive insulating layer formed of a ferroelectric layer or a high dielectric layer.
SOLUTION: The semiconductor memory device is equipped with insulating layers 5 and 11 formed on a semiconductor substrate 1; a first plug 15 formed inside a first hole 12 bored in the layers 5 and 11; a first insulating hydrogen barrier 17 which is formed on the insulating layers 5 and 11, and equipped with a second hole 18 communicating with the first hole 12; a second plug 19 formed of a second conductive hydrogen barrier layer formed inside the second hole 18; and a lower electrode 20, a capacitive insulating layer 22, and an upper electrode 23 which are successively formed in this sequence on the first hydrogen barrier layer 17 and the second plug 19. A seam 16 is formed inside the first plug 15, and an insulating material 17a is embedded in a part of the seam 16.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了实现电容器结构的防止，由于在使用由铁电层形成的电容绝缘层的电容器中与下电极电连接的插头上形成的接缝而导致的特性劣化或高介电层。解决方案：半导体存储器件配备有形成在半导体衬底1上的绝缘层5和11; 形成在层5和11中钻孔的第一孔12内的第一塞子15; 形成在绝缘层5和11上并配备有与第一孔12连通的第二孔18的第一绝缘氢阻挡层17; 由形成在第二孔18内的第二导电氢阻挡层形成的第二塞子19; 以及在第一氢阻挡层17和第二插塞19上依次形成的下电极20，电容绝缘层22和上电极23.接缝16形成在第一插塞15的内部，绝缘材料17a嵌入在接缝16的一部分中。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006156932A Dielectric memory and manufacturing method therefor 审中-公开
标题翻译：介电记忆及其制造方法
公开(公告)号：JP2006156932A
公开(公告)日：2006-06-15
申请号：JP2005107900
申请日：2005-04-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKAWA TAKUMI , OKUNI MITSUHIRO , YOSHIDA HIROSHI
IPC分类号： H01L27/105 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To provide a dielectric memory which has a capacitive insulating film showing a superior step coverage, and has a structure enabling microfabrication. SOLUTION: The dielectric memory comprises first lower electrodes 12, a first insulating film 13 having openings 13h that reach the upper surfaces of the first lower electrodes 12, second lower electrodes 14b formed on the walls of the openings 13h, the capacitive insulating film 15 which is so formed above the first and second lower electrodes 12, 14b as not to fill the holes (openings 13h), and an upper electrode 16 formed on the capacitive insulating film 15. The film thickness of the second lower electrodes 14b to that of the openings 13h is made greater at the lower part than the upper part of the openings 13h. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有优异的台阶覆盖率的电容绝缘膜的电介质存储器，并且具有能够进行微细加工的结构。解决方案：介质存储器包括第一下电极12，具有到达第一下电极12的上表面的开口13h的第一绝缘膜13，形成在开口13h的壁上的第二下电极14b，电容绝缘薄膜15形成在第一和第二下部电极12,144之上，以不填充孔（开口13h），以及形成在电容绝缘膜15上的上部电极16.第二个下部电极14b至在开口13h的上部比在开口13h的上部更大的部分。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005268494A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005268494A
公开(公告)日：2005-09-29
申请号：JP2004078229
申请日：2004-03-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKAWA TAKUMI , SOSHIRO YUUJI
IPC分类号： H01L27/105 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11502 , H01L21/76895 , H01L27/10814 , H01L27/10882 , H01L27/10894 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/90
摘要： PROBLEM TO BE SOLVED: To materialize a structure leading out the potential of an upper electrode to a diffusion layer, in the dielectrics memory having a solid stack type structure,.
SOLUTION: The semiconductor device is provided with: a first impurity diffused layer 102 and a second impurity diffused layer 103 mutually separated and formed on a semiconductor substrate 100; a first interlayer insulating film 104; a first contact plug 106; a second interlayer insulating film 110; a first opening 110a; and a capacitative element comprising a first metal film (lower electrode) 111 electrically connected with the upper edge of the first contact plug 106 at the wall and the bottom of the first opening 110a, a ferroelectric film (capacity insulating film) 112, and a second metal film (upper electrode) 113. Moreover, the second impurity diffused layer 103 and the upper electrode 113 are electrically connected via the second metal film 113 formed at the wall and the bottom of the second contact plug 107 and a second opening 110b.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在具有固体堆叠型结构的电介质存储器中，实现导致上电极到扩散层的电位的结构。解决方案：半导体器件设置有：在半导体衬底100上相互分离并形成的第一杂质扩散层102和第二杂质扩散层103; 第一层间绝缘膜104; 第一接触插塞106; 第二层间绝缘膜110; 第一开口110a; 以及电容元件，包括在第一开口110a的壁和底部与第一接触插头106的上边缘电连接的第一金属膜（下电极）111，铁电膜（电容绝缘膜）112和第二金属膜（上电极）113。此外，第二杂质扩散层103和上电极113经由形成在第二接触插塞107的壁和底部的第二金属膜113和第二开口110b电连接。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005150339A Electrode forming method, capacitor element, and its manufacturing method 审中-公开
标题翻译：电极形成方法，电容元件及其制造方法
公开(公告)号：JP2005150339A
公开(公告)日：2005-06-09
申请号：JP2003384788
申请日：2003-11-14
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKAWA TAKUMI , HIRANO HIROSHIGE
IPC分类号： H01L21/768 , H01L21/02 , H01L21/8246 , H01L27/105
CPC分类号： H01L28/92 , H01L28/56 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To microminiaturize electrodes constituting a capacitor element, and to provide a method of manufacturing a capacitor element equipped with the microminiaturized electrodes.
SOLUTION: The method of manufacturing the capacitor element comprises processes of: forming a first conductive film on a semiconductor substrate; forming a first linear mask pattern which extends in a first direction on the first conductive film; etching the first conductive film by the use of the first mask pattern to form a conductive film pattern; forming a dielectric film and a second conductive film successively in this sequence on the semiconductor substrate; forming a second linear mask pattern which extends in a second direction different from the first direction on the second conductive film; and etching the second conductive film, the dielectric film, and the conductive film pattern by the use of the second mask pattern to form the capacitor element composed of a capacitor lower electrode, a capacitor insulating film, and a capacitor upper electrode.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了使构成电容器元件的电极微型化，并且提供一种制造配备有微型电极的电容器元件的方法。解决方案：制造电容器元件的方法包括以下处理：在半导体衬底上形成第一导电膜; 形成在第一导电膜上沿第一方向延伸的第一线性掩模图案; 通过使用第一掩模图案蚀刻第一导电膜以形成导电膜图案; 在该半导体基板上依次形成电介质膜和第二导电膜; 形成在与所述第二导电膜上的所述第一方向不同的第二方向上延伸的第二线状掩模图案; 并通过使用第二掩模图案蚀刻第二导电膜，电介质膜和导电膜图案，以形成由电容器下电极，电容器绝缘膜和电容器上电极组成的电容器元件。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005150262A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005150262A
公开(公告)日：2005-06-09
申请号：JP2003383206
申请日：2003-11-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAGAHASHI KATSUMI , MIKAWA TAKUMI
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To suppress a void occurring in a contact plug connected to a diffusion preventing film below a lower electrode whose upper end constitutes a ferroelectric capacitor, and to prevent deterioration of an electric characteristic of the ferroelectric capacitor.
SOLUTION: A semiconductor device is provided with an interlayer insulating film 17 laminated on a semiconductor substrate 11, a contact hole formed in the interlayer insulating film 17, the contact plug 22 with which filler is filled, the conductive diffusion preventing film 23 formed on the interlayer insulating film 17 by covering the upper part of the contact plug 22, the lower electrode 24 formed on the diffusion preventing film 23 in order from below, a capacitance insulating film 25 formed of insulating metal oxide, and the upper electrode 26. A side wall 19 is formed on the side wall of the contact hole, and the contact plug 22 is formed on the inner side of the side wall 19.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制与其上端构成铁电电容器的下电极下方的扩散防止膜连接的接触插塞中发生的空穴，并且防止铁电电容器的电特性的劣化。解决方案：半导体器件设置有层叠在半导体衬底11上的层间绝缘膜17，形成在层间绝缘膜17中的接触孔，填充有填充物的接触插塞22，导电扩散防止膜23 通过从下面依次覆盖接触插塞22的上部，形成在防扩散膜23上的下部电极24，由绝缘金属氧化物形成的电容绝缘膜25和上部电极26，形成在层间绝缘膜17上侧壁19形成在接触孔的侧壁上，接触插塞22形成在侧壁19的内侧。（C）2005年，JPO＆NCIPI

9. 发明专利

JP2005011866A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005011866A
公开(公告)日：2005-01-13
申请号：JP2003171802
申请日：2003-06-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NOMA JUNJI , MIKAWA TAKUMI
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To prevent hydrogen from penetrating into a capacitor element through a top surface region of an upper electrode where a hydrogen permeation preventive layer is not provided.
SOLUTION: A semiconductor device comprises a capacitor element 107 composed of a lower electrode 104, a capacitor insulating film 105, and an upper electrode 106 which are successively formed on a first insulating layer 101; an upper insulating hydrogen permeation preventive layer 108 which is formed so as to cover the capacitor element 107, and provided with a first opening 108a that exposes the top surface of the upper electrode 106; and a second insulating layer 109 which is formed on the upper insulating hydrogen permeation preventive layer 108, and provided with a second opening 109a communicating with the first opening 108a. Furthermore, the upper insulating hydrogen permeation preventive layer 108 which is formed in the region where the top surface of the upper electrode 106 is exposed in the openings 18a and 109a, and a wiring layer 111 formed above the upper insulating hydrogen permeation preventive layer 108, are provided.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止氢气通过不设置氢气防止层的上部电极的顶表面区域渗入电容器元件。解决方案：半导体器件包括由下电极104，电容器绝缘膜105和上电极106构成的电容器元件107，其依次形成在第一绝缘层101上; 形成为覆盖电容器元件107并具有暴露上电极106的顶表面的第一开口108a的上绝缘氢防渗层108; 以及第二绝缘层109，其形成在上绝缘氢防渗层108上，并且设置有与第一开口108a连通的第二开口109a。此外，形成在上电极106的顶表面在开口18a和109a中露出的区域中的上绝缘氢防渗层108以及形成在上绝缘氢渗透防止层108上方的布线层111，被提供。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2004221358A Dielectric memory and its manufacturing method 有权
公开(公告)号：JP2004221358A
公开(公告)日：2004-08-05
申请号：JP2003007621
申请日：2003-01-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIKAWA TAKUMI , SOSHIRO YUUJI , NAGANO YOSHIHISA
IPC分类号： H01L27/105 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To provide a dielectric memory which prevents releasing of a lower electrode, an oxygen barrier film and a contact plug interface due to the oxidation of the contact plug of a stack type ferroelectric capacitor or a stress, and which can be highly integrated; and to provide a method for manufacturing the same.
SOLUTION: The dielectric memory includes the lower electrode (3), a capacity insulating film (4), and an upper electrode (5) formed by sequentially laminating them on a substrate (1). The lower electrode (3) is formed by coating the contact plug (6) electrically connected to the substrate (1) to spread in its circumference, and the upper electrode (5) is formed to extend in a first direction (an upper electrode extending direction). The length (lower electrode extending distance) of the lower electrode (3) extending over the contact plug (6) is formed to become longer in a direction perpendicular to the first direction (upper electrode non-extending direction) of the upper electrode (5) than the first direction.
COPYRIGHT: (C)2004,JPO&NCIPI

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