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1. 发明专利

JP2007274444A Ad converter checking apparatus 审中-公开
标题翻译： AD转换器检查装置
公开(公告)号：JP2007274444A
公开(公告)日：2007-10-18
申请号：JP2006098813
申请日：2006-03-31
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MASUNARI KUNIYUKI
IPC分类号： H03M1/10 , G01R31/316
摘要： PROBLEM TO BE SOLVED: To provide a checking method in an A-D converter which inputs a high frequency signal and performs high-speed sampling operation.
SOLUTION: The present invention relates to an A-D converter checking apparatus in which analog signals A and B are inputted to an A-D (analog-digital) converter 1 and an A-D converter 2, respectively, a multiplication clock is generated using a PLL (Phase Locked Loop) 6 to a signal converted into a digital signal by the A-D converter 2, that the generated clock is supplied to the A-D converter 1 to be checked, the same clock is supplied to the A-D converter 2 and it can be discriminated by a detector 3 whether the A-D converter 1 normally operates, using an output signal of the A-D converter 1 to be checked.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供输入高频信号并执行高速采样操作的A-D转换器中的检查方法。解决方案：本发明涉及一种AD转换器检查装置，其中模拟信号A和B分别被输入到AD（模拟 - 数字）转换器1和AD转换器2，使用PLL产生乘法时钟（锁相环）6发送到由AD转换器2转换成数字信号的信号，将生成的时钟提供给要被检查的AD转换器1，将相同的时钟提供给AD转换器2，并且可以被识别通过检测器3，AD转换器1是否正常工作，使用要检查的AD转换器1的输出信号。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007273016A Reproduction signal processor 审中-公开
标题翻译：生殖信号处理器
公开(公告)号：JP2007273016A
公开(公告)日：2007-10-18
申请号：JP2006098812
申请日：2006-03-31
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MASUNARI KUNIYUKI , OGURA YOICHI , NAKAJIMA TAKESHI , MIYASHITA SEIJUN
IPC分类号： G11B20/10 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To solve the following problem: an information decoder operating at high speed is needed in order to speed up a data transfer rate of a digital information recorder and this invites increases in circuit scale, power consumption, and decoding delay.
SOLUTION: A PRML information processor 8 for reducing power consumption and deleting decoding delay while improving reproduction performance by using a PR equalizer 5 for performing PR equalization by using data delayed in 1/2 phase with respect to information which has digitized reproduction waveform obtained from a recording medium 1 by an A/D (analog/digital) converter 4, an adaptive equalization coefficient calculator 6 for learning a filter coefficient adaptively in the PR equalizer, and a viterbi decoder 7 for performing maximum likelihood decoding that reduces a path memory length by sorting out an output result from a path memory with respect to the equalization waveform.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决以下问题：为了加快数字信息记录器的数据传送速率，需要高速运行的信息解码器，并且这增加了电路规模，功耗和解码延迟。解决方案：一种用于降低功耗并删除解码延迟的PRML信息处理器8，同时通过使用用于执行PR均衡的PR均衡器，通过使用具有数字化的再现波形的信息的1/2阶段延迟的数据来提高再现性能通过A / D（模拟/数字）转换器4从记录介质1获得的自适应均衡系数计算器6，用于在PR均衡器中自适应地学习滤波器系数;以及维特比解码器7，用于执行减少路径的最大似然解码存储器长度，通过从路径存储器输出相对于均衡波形的输出结果。版权所有（C）2008，JPO＆INPIT

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