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1. 发明专利

JP2008153425A Manufacturing method of semiconductor chip 有权
标题翻译：半导体芯片的制造方法
公开(公告)号：JP2008153425A
公开(公告)日：2008-07-03
申请号：JP2006339677
申请日：2006-12-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , HAJI HIROSHI
IPC分类号： H01L21/52 , H01L21/301
CPC分类号： H01L24/29 , H01L24/27 , H01L2224/83191
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor chip, capable of preventing a wire bonding electrode on a press-fitting head or a semiconductor chip from being contaminated due to a die attach film flowing from the external edge of the semiconductor chip and moving up to the upper surface of the semiconductor chip, in joining the semiconductor chip to a surface to be joined.
SOLUTION: In this manufacturing method, a thermosetting progressing step S5 for progressing heat curing of a cutting margin both-side region 2b corresponding to the vicinity of a die attach film 5 provided on each semiconductor chip 1' after dicing step S8 on the outside of a cutting margin region 2a is executed between a film layer pasting step S3 of pasting a film layer 7 consisting of the die attach film 5 and a UV tape 6 for protecting its outer surface on the semiconductor wafer 1; and the dicing step S8 for removing the cutting margin region 2a of a predetermined width along the dicing line 2 from the semiconductor wafer 1 having the film layer 7 pasted thereon and cutting the semiconductor wafer 1 into a plurality of semiconductor chips 1'.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体芯片的制造方法，能够防止压配头或半导体芯片上的引线接合电极由于从外部边缘流动的管芯附着膜而被污染半导体芯片，并且在将半导体芯片接合到要接合的表面的同时向半导体芯片的上表面移动。解决方案：在该制造方法中，在切割步骤S8之后，在与设置在每个半导体芯片1'上的管芯附着膜5相邻的切割边缘两侧区域2b进行热固化的热固化步骤S5 切割边缘区域2a的外部在粘贴由管芯附着膜5构成的膜层7的膜层粘贴步骤S3和用于保护半导体晶片1的外表面的UV带6之间执行; 以及切割步骤S8，用于从具有粘贴在其上的膜层7的半导体晶片1沿着切割线2去除具有预定宽度的切割边缘区域2a，并将半导体晶片1切割成多个半导体芯片1'。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007329307A Surface modifying method 审中-公开
标题翻译：表面改性方法
公开(公告)号：JP2007329307A
公开(公告)日：2007-12-20
申请号：JP2006159451
申请日：2006-06-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MORISAKO ISAMU , ARITA KIYOSHI , HAJI HIROSHI
IPC分类号： H01L21/56
CPC分类号： H01L2224/48091 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a surface modifying method which can obtain a suitable surface modifying effect with a low-cost process. SOLUTION: A surface modifying process of processing a mounting object 4 includes a substrate having an insulating film of a resin such as polyimide formed thereon, and also includes a semiconductor chip mounted on the substrate for the purpose of increasing an adhesion between the insulating film and the sealing resin. The mounting object 4 is accommodated in a vacuumed processing chamber 7 of a surface modifying apparatus 5, to cause hydrogen atoms generated from a hydrogen gas by a hydrogen atom generating device 20 to come into contact with the resin surface of the insulating film of the mounting object 4. The chemical bonding on the resin surface is cut off by the activating action of hydrogen atoms, thus generating a hydrophilic reaction group such as a carbonyl group on the resin surface and increasing a wetting property. Consequently, the surface modifying effect can be obtained by the low-cost process more suitably than the prior art surface modifying effect based on a plasma process. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够以低成本的方法获得合适的表面改性效果的表面改性方法。解决方案：处理安装对象物4的表面修饰工艺包括具有在其上形成的聚酰亚胺等树脂的绝缘膜的基板，还包括安装在基板上的半导体芯片，目的在于提高绝缘膜和密封树脂。安装对象4容纳在表面改性装置5的真空处理室7中，以使氢原子产生装置20从氢气产生的氢原子与安装的绝缘膜的树脂表面接触对象4.树脂表面上的化学键被氢原子的活化作用所切断，从而在树脂表面产生亲水性反应基团如羰基，增加润湿性能。因此，与现有技术的基于等离子体处理的表面改性效果相比，可以通过低成本的方法获得表面改性效果。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007266422A Method for manufacturing semiconductor component, and semiconductor device 有权
标题翻译：制造半导体元件的方法和半导体器件
公开(公告)号：JP2007266422A
公开(公告)日：2007-10-11
申请号：JP2006091200
申请日：2006-03-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAJI HIROSHI , ARITA KIYOSHI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/27 , H01L24/83 , H01L2224/32145 , H01L2224/32225 , H01L2224/83 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/351 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor component capable of providing a laminated structure with a plurality of semiconductor components overlapped, and to provide a semiconductor device with the semiconductor component laminated. SOLUTION: The method for manufacturing the semiconductor component for dividing the semiconductor wafer 1 into individual semiconductor elements 1a comprises the steps of forming a groove 1d for half cutting the wafer 1 on the surface opposite to the circuit forming surface, dividing the wafer 1 into individual piece by covering except an opening 12 having a width wider than the groove 1d by a mask 11 and providing an isotropic etching to the opening 12 by a fluorine plasma, and forming a step part 1e with an outer edge of the semiconductor elements 1a removed by the concave shape cross section having the removing thickness d by removing the range to be etched in a concave cross section by the predeterined removing depth d. The steps 1e is used as a runout space of the connection part for a wire bonding. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体部件的制造方法，该半导体部件能够提供重叠的多个半导体部件的叠层结构，并且提供层压有半导体部件的半导体器件。解决方案：将用于将半导体晶片1分割为单独的半导体元件1a的半导体部件的制造方法包括以下步骤：在与电路形成表面相对的表面上形成用于半切割晶片1的槽1d，分割晶片 1通过掩模除去具有比凹槽1d宽的宽度的开口12，并通过氟等离子体对开口12进行各向同性蚀刻，并且形成具有半导体元件的外边缘的台阶部分1e 1a通过具有去除厚度d的凹形截面去除，通过除去预定去除深度d在凹截面中去除蚀刻范围。步骤1e用作引线接合用连接部的跳动空间。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007142297A Method of manufacturing package component 有权
标题翻译：制造包装组件的方法
公开(公告)号：JP2007142297A
公开(公告)日：2007-06-07
申请号：JP2005336562
申请日：2005-11-22
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI
IPC分类号： H01L21/56
CPC分类号： H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/19105 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing package components which forms sealing resin only in a sealing target range with proper adhesion. SOLUTION: The package component manufacturing method covers an electronic component 2, mounted on a substrate 1 with a sealing resin 18 to form a package component. After mounting electronic components 2, 3 on the substrate 1, the surface of the substrate 1 is reformed by a plasma process, to improve the wettability of the surface. An atmospheric pressure plasma unit 12 sprays an atmospheric pressure plasma jet 14a by using fluorine gas on a liquid repelling region set at the marginal edge of a sealing range with the sealing resin 18 on the reformed surface of the substrate 1, thereby causing the surface wettability of the liquid-repelling region to decrease. This prevents the seal resin 18 from expanding its wet zone from the sealing target range of the sealing resin 18, thus forming the sealing resin 18 only in the sealing target range with proper adhesion. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造仅在适当粘合的密封目标范围内形成密封树脂的封装部件的方法。解决方案：封装部件制造方法包括用密封树脂18安装在基板1上以形成封装部件的电子部件2。在基板1上安装电子部件2,3之后，通过等离子体处理使基板1的表面重新形成，以提高表面的润湿性。大气压等离子体单元12通过在设置在密封范围的边缘的液体排斥区域上的氟气喷射大气压等离子体射流14a与基板1的重整表面上的密封树脂18，从而使表面润湿性的排斥区域减少。这样可防止密封树脂18将其湿区从密封树脂18的密封目标范围扩大，从而仅在密封目标范围内形成密封树脂18，同时具有适当的粘附力。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2007019386A Method of manufacturing semiconductor chip 有权
标题翻译：制造半导体芯片的方法
公开(公告)号：JP2007019386A
公开(公告)日：2007-01-25
申请号：JP2005201536
申请日：2005-07-11
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI
IPC分类号： H01L21/301 , H01L21/304
CPC分类号： H01L21/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor chips by which dicing is carried out without causing quality deterioration due to deposited particles. SOLUTION: In the method of manufacturing the semiconductor chips for manufacturing the semiconductor chips 1d by dividing a semiconductor wafer into each semiconductor device, a mask 3 formed for plasma dicing in which the semiconductor wafer is divided by plasma etching is removed by mechanical grinding using a grinding head 26. Thus, occurrence is prevented in reaction products inevitable when removing the mask by plasma ashing, so that dicing is carried out without occurrence of quality deterioration due to the deposited particles. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体芯片的方法，通过该方法进行切割，而不会由于沉积的颗粒而导致质量劣化。解决方案：在通过将半导体晶片分成每个半导体器件来制造用于制造半导体芯片1d的半导体芯片的方法中，通过机械去除用于等离子体切割形成的半导体晶片被等离子体蚀刻分割的掩模3 因此，通过等离子体灰化除去掩模时，防止反应产物的发生变得不可避免，从而进行切割而不会由于沉积的颗粒而导致质量恶化。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006287152A Plasma processing device 有权
标题翻译：等离子体加工装置
公开(公告)号：JP2006287152A
公开(公告)日：2006-10-19
申请号：JP2005108385
申请日：2005-04-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , NAKAGAWA AKIRA
IPC分类号： H01L21/3065
CPC分类号： H01J37/32532 , H01J37/3244 , H01J37/32449
摘要： PROBLEM TO BE SOLVED: To provide a plasma processing device for performing a uniform plasma treatment stably by protecting a porosity board constituting a counter electrode from damage, such as a crack at outer boundary part caused by thermal expansion accompanied by a rapid rise of temperature at the plasma treatment step.
SOLUTION: The plasma processing device has a stage 31 of a lower electrode 3, an upper electrode 4 opposite to the lower electrode, and a processing chamber 2 in which the lower electrode and the upper electrode 4 are arranged. A gas is fed to a plasma processing space A between the lower electrode and the upper electrode 4 for subjecting a treating object W on the stage 31 to perform plasma processing in the plasma processing device. The upper electrode 4 is composed of a main body unit 41 having a gas feeding opening T, a breathable porous board arranged on a lower side of the main body unit 41 for blocking the gas feeding opening T, and a supporting member 45 for supporting an outer edge of a porous board 43. At an outer boundary part of the porous board 43, each slit S is formed at intervals for absorbing distortion caused by thermal expansion at the plasma processing.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种等离子体处理装置，其通过保护构成对置电极的孔隙率基板等的均匀等离子体处理来进行均匀的等离子体处理，以免由伴随着快速上升的热膨胀引起的外部边界部分的裂纹的等离子体处理步骤的温度。解决方案：等离子体处理装置具有下电极3的阶段31，与下电极相对的上电极4，以及配置有下电极和上电极4的处理室2。将气体供给到下电极和上电极4之间的等离子体处理空间A，用于对载物台31上的处理对象W进行等离子体处理装置中的等离子体处理。上电极4由具有供气口T的主体单元41，设置在主体单元41的下侧的用于阻塞气体供给口T的透气性多孔板构成，以及支撑构件45 多孔板43的外边缘。在多孔板43的外边界部分处，间隔地形成每个狭缝S，用于吸收等离子体处理时的热膨胀引起的变形。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006128161A Light emitting element mounting structure and method of manufacturing the same 有权
标题翻译：发光元件安装结构及其制造方法
公开(公告)号：JP2006128161A
公开(公告)日：2006-05-18
申请号：JP2004310515
申请日：2004-10-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHIKAWA TAKATOSHI , ARITA KIYOSHI , HAJI HIROSHI
IPC分类号： H01L33/62 , H01L33/64
摘要： PROBLEM TO BE SOLVED: To provide a light emitting element mounting structure which can realize the improvement in heat dissipation with stable reliability, and to provide a method of manufacturing the light emitting element mounting structure.
SOLUTION: In the light emitting element mounting structure, an n-type semiconductor 3 is formed to cover the whole surface on a sapphire substrate 2, an n-type semiconductor 4 and a p-type semiconductor 5 are formed on the top surface of the n-type semiconductor 3, and further an LED 1 of the configuration that a p-type electrode 6 is formed on the top surface of the p-type semiconductor 5 is packaged in a substrate 7. A conductor layer 22a is formed by coating and curing metal nano particle paste to the n-type electrode 4, and the conductor layer 22a is connected to the first terminal 9a of the substrate 7 at the packaging time by positioning and bonding the p-type semiconductor 5 to the second terminal 9b. Consequently, the LED 1 can be packaged in the substrate 7 by a thin bonding part in a large bonding area as much as possible, and the improvement in the heat dissipation can be realized with stable reliability.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够以稳定可靠性实现散热改善的发光元件安装结构，并且提供一种制造发光元件安装结构的方法。解决方案：在发光元件安装结构中，形成n型半导体3以覆盖蓝宝石衬底2上的整个表面，在顶部形成n型半导体4和p型半导体5 n型半导体3的表面，以及在p型半导体5的上表面上形成p型电极6的另外的LED1被封装在基板7中。形成导体层22a 通过将金属纳米颗粒糊涂布并固化到n型电极4上，并且在封装时通过将p型半导体5定位并接合到第二端子而将导体层22a连接到基板7的第一端子9a 9B。因此，LED1可以通过尽可能大的接合区域中的薄接合部封装在基板7中，并且可以以稳定的可靠性实现散热的改善。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006066601A Jig for component conveyance 有权
标题翻译：用于组件输送
公开(公告)号：JP2006066601A
公开(公告)日：2006-03-09
申请号：JP2004246705
申请日：2004-08-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , HAJI HIROSHI
IPC分类号： H01L21/673 , H01L21/50
摘要： PROBLEM TO BE SOLVED: To provide a jig for component conveyance in which components which are divided into pieces and are held in a sheet are stably kept and they can easily be handled. SOLUTION: In a carrier 7 conveying LED elements 2 which are divided into pieces by dicing and are stuck and held on the sheet 1, an opening 7b where the LED elements 2 held by the sheet 1 are exposed upward is arranged in a tabular main body 7a having a planar external form larger than an external form of the sheet 1. A sheet holder 7c where a sticking face 7d to which the adhesion layer 1a of the sheet 1 is stuck is installed on the lower face of the main body 7a at a periphery of the opening 7b is protrusively disposed downward. Lower sides on both ends of the main body 7a are set to be conveyance support faces 7f supported by a conveyance mechanism 8, and side end faces are used as conveyance guide faces 7e guiding the main body in a horizontal direction. Thus, the LED elements 2 in a piece state held by the sheet 1 can stably be held and they can easily be handled. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于部件传送的夹具，其中被分割成片并被保持在片材中的部件被稳定地保持并且它们可以容易地被处理。解决方案：在传送LED元件2的载体7中，通过切割分割成块并被卡住并保持在片材1上，由片材1保持的LED元件2向上露出的开口7b布置在片状主体7a具有比片材1的外形更大的平面外形。片材保持器7c安装在主体的下表面上，片材1的粘合层1a被粘贴在其上的粘着面7d 7a的开口7b的周边突出地向下设置。将主体7a的两端的下侧设置为由输送机构8支撑的输送支撑面7f，并且将侧端面用作沿水平方向引导主体的输送引导面7e。因此，可以稳定地保持由片材1保持的片状状的LED元件2，并且它们可以容易地被处理。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2004175591A Apparatus and method of dry-etching piezoelectric substrate preform, piezoelectric substrate preform, piezoelectric vibration element and piezoelectric device 有权
公开(公告)号：JP2004175591A
公开(公告)日：2004-06-24
申请号：JP2002340940
申请日：2002-11-25
申请人： Matsushita Electric Ind Co Ltd , Toyo Commun Equip Co Ltd , 東洋通信機株式会社 , 松下電器産業株式会社
发明人： ARITA KIYOSHI , MATSUKI KIYOTAKA
IPC分类号： C30B33/08
摘要： PROBLEM TO BE SOLVED: To provide a dry-etching apparatus or the like capable of forming a semi-spherical (convex lens like) projecting part provided with a desired loose curved shape on one surface center part of a piezoelectric substrate such as an AT cut quartz crystal substrate for the first time by the dry-etching method without using a resist causing the increase of percent defective after etching.
SOLUTION: The dry-etching apparatus for forming a plurality of the semi-spherical projecting parts 52 on one main surface of a piezoelectric substrate preform 51 is provided with a 1st electrode 11 provided with a supporting surface 12 attracting the piezoelectric substrate preform, a 2nd electrode 21, a vacuum vessel 31, a gas supply means 35 for supplying an etching gas into the vacuum vessel 31, a high frequency power source 40 and a negative pressure producing means 14 for attracting and holding the piezoelectric substrate preform on the supporting surface by introducing the negative pressure to each sucking port provided on the supporting surface of the 1st electrode and each suction port is arranged at a position corresponding to a plurality of the semi-spherical projecting parts formed on one main surface of the piezoelectric substrate preform.
COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2003318161A Device and method for plasma treatment 有权
标题翻译：用于等离子体处理的装置和方法
公开(公告)号：JP2003318161A
公开(公告)日：2003-11-07
申请号：JP2003157934
申请日：2003-06-03
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , IWAI TETSUHIRO , TERAYAMA JUNICHI
IPC分类号： H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide a device and method for plasma treatment by which the occurrence of failures can be prevented by holding a semiconductor substrate with sufficient electrostatic holding power. SOLUTION: In the plasma treatment device which performs plasma treatment on a silicon wafer 6 while a protective tape 6a is stuck to the circuit forming surface of the wafer 6, the wafer 6 is placed on a placing surface 3d on the upper surface of a lower electrode 3 made of a conductive metal, with the protective tape 6a on the placing surface 3d side. When the wafer 6 is held by the lower electrode 3 by electrostatic attraction by impressing a DC voltage upon the electrode 3 from a DC power source section 18 for electrostatic attraction at the time of performing the plasma treatment, the protective tape 6a is utilized as a dielectric for electrostatic attraction. Consequently, the silicon wafer 6 can be held with sufficient electrostatic holding power, because the thickness of the can be reduced to the utmost. COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：提供一种用于等离子体处理的装置和方法，通过该装置和方法可以通过保持具有足够的静电保持力的半导体衬底来防止故障的发生。解决方案：在将保护带6a粘贴到晶片6的电路形成表面的同时对硅晶片6进行等离子体处理的等离子体处理装置中，将晶片6放置在上表面上的放置表面3d上由导电金属制成的下电极3，其中保护带6a位于放置表面3d侧。当通过在进行等离子体处理时从用于静电吸引的直流电源部分18施加直流电压至电极3上的晶片6被下部电极3保持时，保护带6a被用作电介质用于静电吸引。因此，可以将硅晶片6保持在足够的静电保持力，因为可以最大限度地减小厚度。版权所有（C）2004，JPO

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