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1. 发明专利

JP2006040914A Method and device for dicing semiconductor wafer 审中-公开
标题翻译：用于定义半导体波形的方法和装置
公开(公告)号：JP2006040914A
公开(公告)日：2006-02-09
申请号：JP2004213910
申请日：2004-07-22
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , HAJI HIROSHI , NAKAGAWA AKIRA , NODA KAZUHIRO
IPC分类号： H01L21/301
摘要： PROBLEM TO BE SOLVED: To ensure high flexural strength in dicing of a semiconductor wafer rendered thin, without damaging each semiconductor element. SOLUTION: In a semiconductor wafer 6 where a protective sheet 30 is arranged on the first surface 6a, where a plurality of semiconductor elements are formed and a mask 31a for defining lines 31b for dicing the semiconductor wafer into individual semiconductor elements is arranged on the second surface 6b opposite to the side of the first surface 6a, the semiconductor wafer is diced into individual semiconductor elements along the defining lines 31b, thus defined by performing plasma etching from the second surface 6b. In the plasma etching, either anisotropic etching or isotropic etching is carried out, followed by the other etching. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了确保半导体晶片的切割中的高弯曲强度，而不损坏每个半导体元件。解决方案：在其上形成有多个半导体元件的第一表面6a上布置保护片30的半导体晶片6和用于将用于将半导体晶片切割成单独的半导体元件的线31b的掩模31a布置在与第一表面6a相对的第二表面6b上，沿着限定线31b将半导体晶片切割成单独的半导体元件，由此通过从第二表面6b执行等离子体蚀刻来限定。在等离子体蚀刻中，进行各向异性蚀刻或各向同性蚀刻，接着进行其他蚀刻。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2008042085A Semiconductor memory device, and its manufacturing method 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2008042085A
公开(公告)日：2008-02-21
申请号：JP2006217222
申请日：2006-08-09
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAGAWA AKIRA , NAKABAYASHI TAKASHI , ARAI HIDEYUKI
IPC分类号： H01L21/8242 , H01L21/768 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10811
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a capacitor which can hold sufficient amount of charge, and to provide a method for manufacturing it. SOLUTION: The semiconductor memory device includes: a transistor formed in a substrate 11; the capacitor formed above one of source region/drain region 14 of the transistor; a bit line 24 which is formed above the substrate 11 and extended in a gate length direction of the transistor; a first conductor plug 16a connecting one of the source region/drain region 14 and the capacitor; a second conductor plug 16b connected to one of the source region/drain region 14 which is not connected to the first conductor plug 16a; and a third conductor plug 21 which is formed on the second conductor plug 16b and connected to the bit line 24. The third conductor plug 21 is so formed that its center axis shifts from a center axis of the second conductor plug 16b in the gate width direction of the transistor. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够保持足够量的电荷的电容器的半导体存储器件，并提供其制造方法。解决方案：半导体存储器件包括：形成在衬底11中的晶体管; 所述电容器形成在所述晶体管的源极区域/漏极区域14之上; 位于衬底11上方并沿晶体管的栅极长度方向延伸的位线24; 连接源区域/漏极区域14和电容器之一的第一导体插头16a; 连接到未连接到第一导体插头16a的源极区域/漏极区域14之一的第二导体插头16b; 以及形成在第二导体插头16b上并连接到位线24的第三导体插塞21.第三导体插塞21形成为使得其中心轴从第二导体插头16b的中心轴线以栅极宽度晶体管的方向。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006287152A Plasma processing device 有权
标题翻译：等离子体加工装置
公开(公告)号：JP2006287152A
公开(公告)日：2006-10-19
申请号：JP2005108385
申请日：2005-04-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , NAKAGAWA AKIRA
IPC分类号： H01L21/3065
CPC分类号： H01J37/32532 , H01J37/3244 , H01J37/32449
摘要： PROBLEM TO BE SOLVED: To provide a plasma processing device for performing a uniform plasma treatment stably by protecting a porosity board constituting a counter electrode from damage, such as a crack at outer boundary part caused by thermal expansion accompanied by a rapid rise of temperature at the plasma treatment step.
SOLUTION: The plasma processing device has a stage 31 of a lower electrode 3, an upper electrode 4 opposite to the lower electrode, and a processing chamber 2 in which the lower electrode and the upper electrode 4 are arranged. A gas is fed to a plasma processing space A between the lower electrode and the upper electrode 4 for subjecting a treating object W on the stage 31 to perform plasma processing in the plasma processing device. The upper electrode 4 is composed of a main body unit 41 having a gas feeding opening T, a breathable porous board arranged on a lower side of the main body unit 41 for blocking the gas feeding opening T, and a supporting member 45 for supporting an outer edge of a porous board 43. At an outer boundary part of the porous board 43, each slit S is formed at intervals for absorbing distortion caused by thermal expansion at the plasma processing.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种等离子体处理装置，其通过保护构成对置电极的孔隙率基板等的均匀等离子体处理来进行均匀的等离子体处理，以免由伴随着快速上升的热膨胀引起的外部边界部分的裂纹的等离子体处理步骤的温度。解决方案：等离子体处理装置具有下电极3的阶段31，与下电极相对的上电极4，以及配置有下电极和上电极4的处理室2。将气体供给到下电极和上电极4之间的等离子体处理空间A，用于对载物台31上的处理对象W进行等离子体处理装置中的等离子体处理。上电极4由具有供气口T的主体单元41，设置在主体单元41的下侧的用于阻塞气体供给口T的透气性多孔板构成，以及支撑构件45 多孔板43的外边缘。在多孔板43的外边界部分处，间隔地形成每个狭缝S，用于吸收等离子体处理时的热膨胀引起的变形。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006015356A Arc welding equipment 有权
标题翻译：弧焊设备
公开(公告)号：JP2006015356A
公开(公告)日：2006-01-19
申请号：JP2004193662
申请日：2004-06-30
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YOSHIDA TAKUMA , NAKAGAWA AKIRA
IPC分类号： B23K9/073 , H02M9/00
摘要： PROBLEM TO BE SOLVED: To provide an arc welding equipment capable of preventing arc cutting and suppressing sputter by controlling the output of an arc control unit to an optimum value during a predetermined period from an instant shifted from a short-circuit state to an arc discharge state.
SOLUTION: The arc welding equipment can control the output of an arc control unit to an optimum value by controlling the resistance between a welding voltage detection unit and a short-circuit control unit to be at least a predetermined value with the time of shift from the arc discharge state to the short-circuit state as a starting point, and controlling the resistance between the welding voltage detection unit and the short-circuit control unit to be substantially zero with the time of shift from the short-circuit state to the arc discharge state as a starting point.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种电弧焊接设备，其能够在从短路状态转移到瞬间的瞬间的预定时段期间将电弧控制单元的输出控制为最佳值，从而防止电弧切割并抑制溅射电弧放电状态。解决方案：电弧焊接设备可以通过将焊接电压检测单元和短路控制单元之间的电阻控制为至少预定值来控制电弧控制单元的输出达到最佳值，从电弧放电状态切换到短路状态为起点，并且将焊接电压检测单元和短路控制单元之间的电阻控制为从短路状态向时间变化的基本为零电弧放电状态为起点。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2003048068A Welding power source device 审中-公开
标题翻译：焊接电源设备
公开(公告)号：JP2003048068A
公开(公告)日：2003-02-18
申请号：JP2001230282
申请日：2001-07-30
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUBO KUNIO , HAMAMOTO YASUSHI , KAWAMOTO ATSUHIRO , YONEMORI SHIGEKI , NAKAGAWA AKIRA
IPC分类号： B23K9/06
摘要： PROBLEM TO BE SOLVED: To easily move a portable welding power source device for a long distance, and to improve the protection and operability of an operation panel when installed on a floor surface.
SOLUTION: The welding power source device with the operation panel 7 mounted on a front plate 8 of a box body 10 having a control unit for controlling the welding output inside thereof comprises a leg for installation on the front surface side of a bottom plate 2 of the box 10, a wheel 3 for movement provided on the rear surface side, a handle 4 expandably fitted in the projecting direction from the front plate 8, and a portable holding part provided on a top plate 6 of the box 10, and the handle 4 is protruded forward of the operation panel 7 in a contracted condition, and surrounds the operation panel 7. The welding power source device can be carried by holding the handle part when moving in a near distance. When moving over a large distance, the expandable handle 4 is expanded and lifted and the welding power source device can be easily moved by the wheel 3. Since an external article hits the handle 4 before it hits the operation panel 7, the operation panel 7 and components thereof can be prevented from being damaged.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：便于长时间移动便携式焊接电源设备，并且当安装在地板表面上时，可以提高操作面板的保护和操作性。解决方案：具有安装在具有用于控制其内部的焊接输出的控制单元的箱体10的前板8上的操作面板7的焊接电源装置包括用于安装在底板2的前表面侧上的支脚盒子10，设置在后表面侧的运动用轮3，从前板8沿伸出方向可膨胀地配合的把手4和设置在盒子10的顶板6上的便携式保持部件，手柄 4在收缩状态下突出到操作面板7的前方，并且围绕操作面板7.焊接电源装置可以通过在近距离移动时保持把手部来承载。当移动较大距离时，可扩展手柄4被膨胀和提升，并且焊接电源装置可以被轮3容易地移动。由于外部物品在撞击操作面板7之前碰到手柄4，所以操作面板7 并且可以防止其组件的损坏。

6. 发明专利

JP2007275995A Method for controlling weld termination process and arc welding machine 有权
标题翻译：焊接终止过程控制方法及电弧焊机
公开(公告)号：JP2007275995A
公开(公告)日：2007-10-25
申请号：JP2007195386
申请日：2007-07-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TANAKA YOSHIRO , KAWAMOTO ATSUHIRO , NAKAGAWA AKIRA , HAMAMOTO YASUSHI , OYAMA HIDETOSHI , MOTOMIYA AKINORI , YONEMORI SHIGEKI , UEDA AKIKO
IPC分类号： B23K9/09 , B23K9/00 , B23K9/12
摘要： PROBLEM TO BE SOLVED: To improve welding quality and welding workability in a weld termination part by controlling droplet formation on a wire tip at the time of weld termination so as to stably make the droplet a proper size in the weld termination control process of consumable electrode type arc welding and consumable electrode type pulse arc welding.
SOLUTION: In the method for controlling weld termination process, an interval for which the supply of output voltage for welding is inhibited is kept between a first weld termination part and a second weld termination part, and output of peak current is inhibited during an interval for which the output of peak current is inhibited including the period before the control over the first weld termination process is completed, and the output voltage for welding by which the first weld termination process is controlled is established as a function of rotating speed of a motor for feeding a welding wire.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过在焊接终止时控制焊丝尖端上的熔滴形成，在焊接端接部分中提高焊接质量和焊接加工性，以便在焊接终止控制过程中稳定地使液滴成为适当的尺寸消耗电极型电弧焊和消耗电极型脉冲电弧焊。解决方案：在用于控制焊接终止处理的方法中，在第一焊接终端部分和第二焊接终止部分之间保持焊接输出电压供应被禁止的间隔，并且峰值电流的输出在在完成对第一焊接终止处理的控制之前的期间，抑制峰值电流的输出的间隔，并且确定控制第一焊接终止处理的焊接的输出电压作为转速的函数用于给焊丝馈电的电机。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006295067A Method of manufacturing semiconductor chip 有权
标题翻译：制造半导体芯片的方法
公开(公告)号：JP2006295067A
公开(公告)日：2006-10-26
申请号：JP2005117239
申请日：2005-04-14
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , NAKAGAWA AKIRA
IPC分类号： H01L21/3065 , H01L21/301
CPC分类号： H01L21/6835 , H01L21/3065 , H01L21/78 , H01L2221/6834 , H01L2221/68354 , H01L2924/30105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip having high flexural strength in a method of manufacturing the semiconductor chip for forming a singulated semiconductor chip by dividing a semiconductor wafer. SOLUTION: Plasma etching is applied from a second surface to a semiconductor wafer in which an insulating film is arranged on a divided region on a first surface and a mask for defining the dividing region is arranged on the second surface as a surface opposite to the first surface, thereby removing a portion equivalent to the divided region and exposing the insulating film from the etching bottom surface, and after that, the plasma etching is continuously executed in a state that the exposed insulating film is charged by ions in plasma, thereby removing each of corner portions contacting with the insulating film, and after that, after removing the mask, plasma etching is performed for the second surface, thereby removing corner portions of the second surface side. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过划分半导体晶片来制造用于形成单个半导体芯片的半导体芯片的方法中具有高弯曲强度的半导体芯片。解决方案：从第二表面向半导体晶片施加等离子体蚀刻，其中绝缘膜布置在第一表面上的分割区域上，并且用于限定分割区域的掩模布置在第二表面上作为相对的表面从而去除与分割区域相当的部分，并使绝缘膜从蚀刻底面露出，之后在暴露的绝缘膜被等离子体中的离子充电的状态下连续进行等离子体蚀刻，从而除去与绝缘膜接触的每个角部，之后，在除去掩模之后，对第二表面进行等离子体蚀刻，从而去除第二表面侧的拐角部分。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006179768A Method for manufacturing semiconductor chip 有权
标题翻译：制造半导体芯片的方法
公开(公告)号：JP2006179768A
公开(公告)日：2006-07-06
申请号：JP2004373022
申请日：2004-12-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , NAKAGAWA AKIRA
IPC分类号： H01L21/301
CPC分类号： H01L21/6835 , H01L21/78 , H01L22/32
摘要： PROBLEM TO BE SOLVED: To divide a semiconductor wafer having a TEG (test element group) formed thereon into semiconductor chip pieces by plasma etching, and also to efficiently remove the TEG. SOLUTION: A method for manufacturing a semiconductor chip includes a step of bonding a protective sheet so as to be contacted with the TEG on a first surface of a semiconductor wafer, a step of locating a mask on the second surface of the wafer opposed to the first surface, a step of dividing element formation regions into individual semiconductor chips by subjecting the second surface with plasma etching to remove parts corresponding to division regions, and a step of removing the TEG together with the protective sheet with the TEG still remaining in the division regions and bonded to the protective sheet by peeling off the protective sheet from the divided semiconductor chips. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过等离子体蚀刻将其上形成有TEG（测试元件组）的半导体晶片分成半导体芯片片，并且还有效地去除TEG。解决方案：一种用于制造半导体芯片的方法包括在半导体晶片的第一表面上接合保护片以与TEG接触的步骤，将掩模定位在晶片的第二表面上的步骤与第一表面相对的步骤是通过用等离子体蚀刻对第二表面进行分离除去与分割区域相对应的部件，将元件形成区域分割成单独的半导体芯片的步骤，以及与TEG一起保留的保护片材一起除去TEG的步骤在分割区域中，通过从分割的半导体芯片剥离保护片而与保护片接合。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2006108339A Method for dividing semiconductor wafer and method for manufacturing semiconductor element 有权
标题翻译：用于分割半导体晶体的方法和制造半导体元件的方法
公开(公告)号：JP2006108339A
公开(公告)日：2006-04-20
申请号：JP2004292181
申请日：2004-10-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAJI HIROSHI , ARITA KIYOSHI , NAKAGAWA AKIRA , NODA KAZUHIRO
IPC分类号： H01L21/301
CPC分类号： H01L21/78
摘要： PROBLEM TO BE SOLVED: To prevent the fragment of a wafer caused by the division of a semiconductor wafer for dividing respective semiconductor elements into pieces from adhering to the respective semiconductor elements which have been divided into the pieces. SOLUTION: Among a plurality of virtual division areas divided by respective virtual division lines disposed in a lattice shape in a semiconductor wafer 1 and a circumferential line as an outer peripheral contour of the wafer, respective areas 5b of a substantially triangle shape divided by the circumferential line and the virtual division lines are formed as removal areas, and a mask 5c is disposed so that the whole surface on a mask disposed side of the semiconductor wafer 1 in the respective removal areas 5b is exposed. plasma etching is performed from the surface on the mask disposed side of the semiconductor wafer 1, and the respective semiconductor elements are divided along a division line 5a. Also, a portion is removed as relevant to the respective removal areas 5b in the semiconductor wafer 1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由半导体晶片划分各个半导体元件而造成的晶片碎片粘附到已被分割成片的各个半导体元件。解决方案：在半导体晶片1中以晶格形状设置的各个虚拟分割线划分的多个虚拟分割区域和作为晶片的外周轮廓的周边线之间划分大致三角形的各个区域5b 通过圆周线和虚拟分割线形成为去除区域，并且设置掩模5c，使得暴露出各个去除区域5b中的半导体晶片1的设置在掩模的侧面上的整个表面。从半导体晶片1的掩模配置侧的表面进行等离子体蚀刻，并且沿分割线5a划分各个半导体元件。此外，与半导体晶片1中的相应去除区域5b相关的部分被去除。版权所有（C）2006，JPO和NCIPI

10. 发明专利

JP2006066663A Semiconductor package component 审中-公开
标题翻译：半导体封装组件
公开(公告)号：JP2006066663A
公开(公告)日：2006-03-09
申请号：JP2004247769
申请日：2004-08-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAJI HIROSHI , ARITA KIYOSHI , NAKAGAWA AKIRA , NODA KAZUHIRO , NISHINAKA TERUAKI
IPC分类号： H01L21/52
CPC分类号： H01L24/32 , H01L24/743 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/743 , H01L2924/10158 , H01L2924/15787 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element mounting structure for a semiconductor package component in which a semiconductor element is bonded to the surface of an element mount via a bonding material, and which improves the structural strength of the semiconductor package component. SOLUTION: In the mounting structure, the semiconductor package component includes a curved projecting face formed on the end of the mounting side surface of the semiconductor element, and a bonding material filling space which is formed between the curved projecting face covering the entire periphery of the semiconductor element and the surface of the element mount. The bonding material filling space is filled with the bonding material to provide the mounting structure. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了提供半导体封装部件的半导体元件安装结构，其中半导体元件经由接合材料结合到元件安装件的表面，并且提高半导体封装部件的结构强度。解决方案：在安装结构中，半导体封装部件包括形成在半导体元件的安装侧表面的端部上的弯曲突出面，以及形成在覆盖整个半导体元件的弯曲突出面之间的接合材料填充空间半导体元件的周边和元件安装件的表面。接合材料填充空间填充有接合材料以提供安装结构。版权所有（C）2006，JPO＆NCIPI

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