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1. 发明专利

JP2001022097A TRANSFER MARK STRUCTURE FOR MULTILAYERED WIRING PROCESS AND FORMATION OF TRANSFER MARK FOR MULTILAYERED WIRING PROCESS 失效
公开(公告)号：JP2001022097A
公开(公告)日：2001-01-26
申请号：JP19187599
申请日：1999-07-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： HASHIZUME YASUYUKI , SAKAEMORI TAKAHISA
IPC分类号： H01L23/52 , G03F9/00 , H01L21/027 , H01L21/20 , H01L21/3205 , H01L23/544
摘要： PROBLEM TO BE SOLVED: To avert the influence of dishing at the time of molding of groove patterns for multilayered wiring and to make the reading accuracy of marks for transfer higher and stabler by forming underlay layers right below the marks for transfer as groove- like patterns. SOLUTION: The underlay layers 102 similar to those of the prior art exist on the lower layers of hole patterns 13 shown by diagonal lines in the transfer mark structure 10 for the multilayered wiring process and wiring layers 16 are formed on the underlay layers 102. While the wiring layers 16 are heretofore the regions constituted of one rectangular shape in the prior art, this form is a shape lined up with fine lines at equal intervals. When a CPM processing is executed by depositing >=1 layer of the wiring layers 16 consisting of conductors on the groove-like patterns 12, the front surfaces of the groove-like patterns 12 do not have a wide range of surfaces as those in the prior art and, therefore, the occurrence of the dishing on the polished surfaces may be prevented and eventually, the formation of the smooth surfaces is possible and, therefore, the formation of the hole patterns 13 with the good accuracy is made possible.

2. 发明专利

JPH1027884A MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH1027884A
公开(公告)日：1998-01-27
申请号：JP8790897
申请日：1997-04-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU , SATO SHINICHI , OZAKI KOJI , SAKAEMORI TAKAHISA , TANAKA YOSHINORI
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method which is capable of enhancing the integration of a memory cell array. SOLUTION: A field shielding electrode layer 13 is formed in an element isolating region on the surface of a semiconductor substrate through the intermediary of a first oxide film 12, surrounding a separate active region. After the field shielding electrode layer 13 is covered with an insulating film, the word line 8 of a transfer gate transistor is formed through the intermediary of a second insulating film. The word line is made to extend over the field shielding electrode in the element isolating region.

3. 发明专利

JPH09107103A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09107103A
公开(公告)日：1997-04-22
申请号：JP26309695
申请日：1995-10-11
申请人： MITSUBISHI ELECTRIC CORP
发明人： SAKAEMORI TAKAHISA , OOASHI TOSHIYUKI , SHIMOMURA KENICHI
IPC分类号： H01L21/762 , H01L21/76 , H01L21/822 , H01L27/04 , H01L27/12 , H01L29/423 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To prevent a substrate not grounded, reduce gate capacitance and contact resistance, and provide an SOI-MOS transistor two or more of which can be connected in series. SOLUTION: An active region 5 is divided, by first and second wiring patterns 1 and 2, and third and fourth patterns 14 and 15 extended from one sides thereof, into a pair of n type source and drain regions 3 and p type channel potential fixing regions 4. Holes accumulated in effective channel regions 11 flow into the respective p type channel potential fixing regions 4, thereby enabling prevention a substrate not grounded. Since one of the pair of the n type source and drain regions 3 is broader than the other regions, its contact resistance can be reduced. Since source wiring lines are not mutually connected, further, transistor serial connection can be realized.

4. 发明专利

JPH0571174B2 失效
公开(公告)号：JPH0571174B2
公开(公告)日：1993-10-06
申请号：JP18881786
申请日：1986-08-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： SATO SHINICHI , OZAKI KOJI , SAKAEMORI TAKAHISA
IPC分类号： H01L21/336 , H01L21/28 , H01L29/78 , H01L29/784

5. 发明专利

JPH04247663A FIELD-EFFECT ELEMENT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04247663A
公开(公告)日：1992-09-03
申请号：JP1358891
申请日：1991-02-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： SAKAEMORI TAKAHISA , OKUMURA YOSHIKI
IPC分类号： H01L21/316 , H01L21/76 , H01L29/78
摘要： PURPOSE:To prevent the threshold voltage of a field-effect element from rising and to prevent effectively a reduction in the current driving capacity of the element by a method wherein the channel region is formed into the form of a curved surface in the gate width direction. CONSTITUTION:Element isolation oxide films 2 are formed on a silicon substrate 1 at a prescribed interval, channel cut layers 5 are respectively formed under the lower parts of the films 2, a gate oxide film 3 is formed on the surfaces of the films 2 and the surface of the substrate 1 and a word line (a gate electrode) 4 is formed on the film 3. Here, the form of the surface of the substrate 1, which is positioned between the element isolation regions 2, is formed into an inverted U-shaped type.

6. 发明专利

JPH02191340A FIELD EFFECT SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02191340A
公开(公告)日：1990-07-27
申请号：JP5661189
申请日：1989-03-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： SATO SHINICHI , WAKAMIYA WATARU , SAKAEMORI TAKAHISA , OZAKI KOJI , TANAKA YOSHINORI
IPC分类号： H01L21/265 , H01L21/336 , H01L29/423 , H01L29/78
摘要： PURPOSE:To obtain a field effect semiconductor device which is free from the influence of hot electrons trapped by a side wall insulating film and has excellent characteristics such as a mutual conductance by a method wherein both low impurity concentration diffused layers and high impurity concentration diffused layers are extended to the part under the side part of a gate electrode. CONSTITUTION:An LDD-MOS transistor includes a pair of low impurity concentration n-type diffused layers 5a and 5b formed in the main surface of a semiconductor substrate 1 and a pair of high impurity concentration n-type diffused layers 6a and 6b. In this transistor, as both the n-type diffused layers 5b and 6b of which a drain is composed are extended to the part under the side part of a lower electrode 22 of which a gate electrode 2 is composed, even if the impurity concentration of the low impurity concentration n-type diffused layer 5b is effectively lowered by trapping of produced hot electrons by a side wall insulating film 4 and a gate insulating film 3, the gate electrode 2 can overlap the drain with the high impurity concentration n-type diffused layer 6b. Therefore, the increase of a source resistance, deterioration of a mutual conductance, etc., which are caused by the effective reduction of the concentration of the low impurity concentration n-type diffused layer can be obtained.

7. 发明专利

JPH0294472A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0294472A
公开(公告)日：1990-04-05
申请号：JP24767088
申请日：1988-09-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： OZAKI KOJI , SAKAEMORI TAKAHISA , TANAKA YOSHINORI , WAKAMIYA WATARU , SATO SHINICHI
IPC分类号： H01L21/3205 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417
摘要： PURPOSE:To lower the resistance of wirings while flattening the wirings by a method wherein the third conductor layers to be formed on impurity regions are formed to be selectively buried in the positions between the first conductivity type layer and the second conductivity type layers. CONSTITUTION:An N channel type MOS transistor is composed of transfer gates 4 and N type impurity diffused regions 60a, 60b to be source/drain regions. Next, tungsten buried layers 19a, 19b are buried in the exposed positions of a substrate 1 to be filled therein between the transfer gates 4 and isolating gates 16 on the surfaces of the N type impurity diffused regions 60a, 60b thereby flattening the whole surface. Furthermore, the tungsten buried layers 19a, 19b are formed to be electrically connected at the small contact gate intervals on the surface of the N type impurity diffused regions 60a, 60b so that the resistance of wirings to the source/drain region may be lowered.

8. 发明专利

JPS60250665A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS60250665A
公开(公告)日：1985-12-11
申请号：JP10683884
申请日：1984-05-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： NISHIMURA TADASHI , SAKAEMORI TAKAHISA
IPC分类号： G11C11/401 , G11C11/00 , H01L21/8242 , H01L21/84 , H01L27/10 , H01L27/108 , H01L29/00 , H01L29/78
摘要： PURPOSE:To prevent a capacity from decreasing due to microminiaturization by providing a memory capacity, and the second conductor layer through a thick insulating film on the memory on the first semiconductor substrate as a switching transistor. CONSTITUTION:An electrode polysilicon 4 is superposed on a thin oxide film 2 separated by a thick oxide film 3 on an Si substrate 1 to form a capacity. Further, an Si layer is superposed by recrystallization of polysilicon on a thick insulator layer 5 to form a MOSFET 7. Drain and polysilicon 4 are filled in a through hole of the insulator 5, connected with the silicide 6 of high melting point metal, and bit wirings 8 for applying a signal to a source and aluminum word wiring 10 for applying a signal to the electrode 9 are provided. The electrode 9 and the word wirings are connected via the through hole, and the bit wirings 8, the wirings 10 and the gate electrode 9 are connected via the through hole, and the wirings 8, 10, and the electrode 9 are insulated by insulators 33, 34. In this memory device, similar function to the conventional memory of this type is obtained, and the area of the capacity can be increased. Accordingly, it can prevent the capacity from decreasing due to microminiaturization, thereby obtaining accurate memory device.

9. 发明专利

JPS6037735A FINE PATTERN FORMATION 失效
公开(公告)号：JPS6037735A
公开(公告)日：1985-02-27
申请号：JP14752883
申请日：1983-08-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAKAJIMA MASAYUKI , SATOU SHINICHI , SAKAEMORI TAKAHISA , ITAKURA HIDEAKI , YONEDA MASAHIRO , MIYAKE KUNIAKI
IPC分类号： H01L21/30 , H01L21/027 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To easily obtain flattened film having least stepped portions by providing an extra light source which is used for obliquely irradiating porjected pattern from the external side in addition to the main light source which is used for vertically projection and exposing a mask pattern onto the sensitive material in the exposing process utilizing photomechanical process technology. CONSTITUTION:The light of a main light source 1 is converted to the parallel light through a main parallel light optical system 3, a reticle 5 providing a mask pattern is irradiated with such parallel light, and the output light thereof is sent to a photosensitive material formed on a semiconductor wafer 7 through a reduction optical system 6. In such constitution, a couple of sub-light 2 source are disposed opposingly at the external sides of the parallel light sent from the optical system 3, and the light therefrom is projected to the end part of reticle 5 through the sub-parallel light optical system 4. The end part of such photosensitive material is irradiated with the light transmitted as explained above through the optical system 6 and the end part is inclined, thereby removing the stepped portion.

10. 发明专利

JPH0834299B2 失效
公开(公告)号：JPH0834299B2
公开(公告)日：1996-03-29
申请号：JP16757889
申请日：1989-06-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMYA WATARU , SATO SHINICHI , OZAKI KOJI , SAKAEMORI TAKAHISA , TANAKA YOSHINORI
IPC分类号： H01L21/76 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108

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