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    • 1. 发明专利
    • FORMING METHOD OF CONNECTING PART
    • JPH11265934A
    • 1999-09-28
    • JP6584298
    • 1998-03-16
    • MITSUBISHI ELECTRIC CORP
    • TAWARA KENJI
    • H01L21/768H01L21/28
    • PROBLEM TO BE SOLVED: To prevent etching residues from being left and a tact time from being elongated when a metal wiring is patterned by a method wherein a first and a second barrier metal film located at the base of a connection hole are made equal to each other in thickness by etching. SOLUTION: A first metal wiring 9 is formed on a semiconductor substrate 1 through the intermediary of an insulating film 3, and a second and a third metal wiring, 16 and 23, are successively laminated through the intermediary of interlayer insulating films 10 and 17 respectively. A contact hole 4 provided penetrating through the insulating film 3 is filled with a barrier metal film 5a and a first metal film 6a. A viahole 11 provided penetrating through the interlayer insulating film 10 is filled up with a barrier metal film 12a and a second metal film 13a The barrier metal films 5a and 5b (or 12a, 12b) are equal to each other in thickness and formed on the inner wall and base of the contact hole being ensured of thickness large enough to have an effect that a barrier metal usually has.
    • 7. 发明专利
    • SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
    • JP2000100940A
    • 2000-04-07
    • JP26491698
    • 1998-09-18
    • MITSUBISHI ELECTRIC CORP
    • TERATANI AKIYOSHITAWARA KENJIYOKOI TAKAHIRO
    • H01L21/302H01L21/28H01L21/3065H01L21/768
    • PROBLEM TO BE SOLVED: To obtain a semiconductor device that is equipped with wiring film layers, contact holes that connect wiring film layers together, and other contact holes connected to a semiconductor substrate and capable of restraining the semiconductor substrate located at the base of the contact holes from being overetched when the contact holes are formed at the same time. SOLUTION: A semiconductor device is equipped with a first wiring film 17 formed on a semiconductor board 15, a first interlayer insulating film 18 provided covering the first wiring film 17, a second wiring film 19 formed on the first interlayer insulating film 18, a second interlayer insulating film 20 provided covering the second wiring film 19, a first contact hole 22 that reaches down to the first wiring film 17 penetrating through the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 18, and a second contact hole 23 that reaches down to the semiconductor substrate 15 penetrating through the second interlayer insulating film 20 and the first interlayer insulating film 18, where the top surface of the first interlayer insulating film 18 is made even by flattening the level difference caused by the first wiring film 17.