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1. 发明专利

JP2563685B2 失效
公开(公告)号：JP2563685B2
公开(公告)日：1996-12-11
申请号：JP7157791
申请日：1991-04-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YANO KOSAKU
IPC分类号： H01L21/8229 , H01L27/102 , H01L27/108

2. 发明专利

JPH08125121A SEMICONDUCTOR DEVICE AND PRODUCTION THEREOF 失效
公开(公告)号：JPH08125121A
公开(公告)日：1996-05-17
申请号：JP19882795
申请日：1995-08-03
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SUGIYAMA TATSUO , HIRAO HIDEJI , YANO KOSAKU , NOMURA NOBORU
IPC分类号： H01L21/60 , H01L21/603 , H01L27/00
摘要： PURPOSE: To produce a cumulatively bonded semiconductor device having high bonding strength while decreasing the number of production steps. CONSTITUTION: A first electrode 11 and an insulation film 12 therefor are formed on the surface of a first semiconductor substrate 10. A second electrode 14 and an insulation film 15 therefor are then formed on the surface of a second semiconductor substrate 13. An irregular pattern having saw-tooth cross-section is formed in stripe at a predetermined period on the surface of the first substrate 10 while an irregular saw-tooth pattern, having phase shifted by 180 deg. from that of the first semiconductor substrate 10, is formed in stripe on the surface of the second semiconductor substrate 13. First and second semiconductor substrates 10, 13 are bonded with the irregularities on the surface mating each other.

3. 发明专利

JPH06349815A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH06349815A
公开(公告)日：1994-12-22
申请号：JP5690694
申请日：1994-03-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UEDA SATOSHI , UEDA TETSUYA , YAMANO ATSUHIRO , YANO KOSAKU
IPC分类号： H01L21/316 , H01L21/318 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To prevent discontinuity defects of metal wiring even sintering is performed after forming a passivation film, which is composed of a bottom layer silicon nitride film and a top layer silicon nitride film, on the metal wiring. CONSTITUTION:A plurality of metal wiring 3 are arranged on a semiconductor substrate through an interlayer insulating film 4, and the metal wiring 3 are covered with a passivation film 8 composed of a bottom layer silicon oxide film (PSG film) 1 and a top layer silicon nitride film 2. The silicon oxide film 1 is accumulated so as to permit the maximum film thickness (t) of the parts formed on the side planes of the metal wiring 3 to be smaller than the half of the shortest distance between the metal wiring 3. The silicon nitride film 2 is accumulated between silicon oxide film parts formed on the side planes of the metal wiring 3.

4. 发明专利

JPH06302598A FABRICATION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06302598A
公开(公告)日：1994-10-28
申请号：JP8830893
申请日：1993-04-15
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TERAI YUKA , HIRAO HIDEJI , MURAKAMI TOMOYASU , YANO KOSAKU
IPC分类号： H01L21/304 , H01L21/31 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/90
摘要： PURPOSE:To form a flat interlayer insulation film at low temperature by covering the surface of a substrate with alkyl group molecules and irradiating a desired part on the surface of the substrate with an electron beam to desorb the alkyl group thereby rendering that part hydrophilic. CONSTITUTION:A polysilicon wiring 13 is formed on a field oxide 12 deposited on a semiconductor substrate 11. Hexamethyldisilazane vapor is then sprayed to form a silyl group 14 on the field oxide 12 and the surface of the polysilicon wiring 13 thus covering the film surface with an alkyl group, i.e., a methyl group, to render the film surface hydrophobic. Subsequently, only the recess is irradiated with an electron beam to render the surface hydrophilic. The semiconductor substrate 11 is then immersed into a silica supersaturation solution of silicofluoride hydrofluoric acid thus depositing silicon dioxide 15 only in the recess which is not hydrophobic. Subsequently, an interlayer insulation film 16 is deposited thereon thus flattening the interlayer insulation film.

5. 发明专利

JPH06283525A FORMATION OF METAL WIRING 失效
公开(公告)号：JPH06283525A
公开(公告)日：1994-10-07
申请号：JP6854193
申请日：1993-03-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UEDA TETSUYA , YANO KOSAKU , MURAKAMI TOMOYASU , YAMANAKA MICHINARI , HIRAO HIDEJI , NOMURA NOBORU
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
摘要： PURPOSE:To reduce cost, to shorten processes, to prevent the generation of a matching deviation and to improve the reliability of through holes in a multilayer wiring process. CONSTITUTION:A BPSG film 302 is deposited on a silicon substrate 301 and after a first Al-Si-Cu film 303, a W film 304 and a second Al-Si-Cu film 305 are deposited, a resist pattern 306 is formed. The film 305 is first etched, then, the film 304 is etched. The pattern 306 left on a metal wiring is removed. Then, the film 305 is etched and as there is a resist redue part in the central part of the film 305, the residue part works as a mask for the film 305 and a metal pillar is remained. An interlayer insulating film is formed on the metal pillar, an etch-back is applied to the interlayer insulating film until the point of metal pillar is exposed and a second metal wiring 313 is formed.

6. 发明专利

JPH06204346A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06204346A
公开(公告)日：1994-07-22
申请号：JP101893
申请日：1993-01-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MURAKAMI TOMOYASU , YANO KOSAKU
IPC分类号： H01L21/3213 , H01L21/3205 , H01L21/768 , H01L21/90
摘要： PURPOSE:To enable an upper wiring metal to be well connected to a connection hole by a method wherein a non-recessed tungsten is formed inside the connection hole. CONSTITUTION:A diffusion layer 4 is formed on a silicon substrate, and insulating film 2 is deposited, and a connection hole 3 is bored in the insulating film so far as to reach the upside of the diffusion layer 4. Then, a Ti film 5, a TiN film 6, and a Ti film 9 are successively formed, a tungsten 7 is formed, and then all the surface of the tungsten 7 is dry-etched with SF6 to leave tungsten 7' inside the connection hole 3. A this point, SF6 reacts with Ti contained in the surface layer to form a titanium fluoride 10 on the surface of the tungsten 7' to restrain tungsten 7' from being etched. Then, a TiN film and a Ti film left on the insulating film 2 are removed with chlorine-containing gas, then titanium fluoride 10 is removed by physical etching with argon, and a metal wiring 8 formed of titanium nitride, aluminum alloy, and titanium is formed as an upper wiring.

7. 发明专利

JPH05304152A 失效
公开(公告)号：JPH05304152A
公开(公告)日：1993-11-16
申请号：JP10966392
申请日：1992-04-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MURAKAMI TOMOYASU , UEDA TETSUYA , YANO KOSAKU
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To enhance electromigration resistance of a metal wiring formed on a substrate. CONSTITUTION:A silicon oxide film 2 formed on a substrate 1 is sequentially deposited with titanium(Ti), titanium nitride(TiN), and aluminum alloy, which are then etched with a resist as a mask thus forming a metal wiring 3. A laminate of Ti and TiN is then deposited entirely thereon followed by deposition of tungsten on the entire surface by CVD method, and then tungsten and high melting point metal compound are etched anisotropically to leave tungsten on the side wall of the metal wiring 3. Formation of tungsten on the side wall of the metal wiring enhances electromigration resistance of the metal wiring without increasing resistance of the metal wiring remarkably. Furthermore, the metal wiring having rounded upper part provides an appropriate shape for filling the gap between the wirings compactly with an insulation film.

8. 发明专利

JPH05109643A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH05109643A
公开(公告)日：1993-04-30
申请号：JP27081991
申请日：1991-10-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MURAKAMI TOMOYASU , YANO KOSAKU , UEDA TETSUYA , UEDA SATOSHI
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522
摘要： PURPOSE:To enable a contact resistance between a diffusion layer which is formed on a semiconductor substrate and a wiring metal to be reduced. CONSTITUTION:A first n-type diffusion layer 5 is formed on a silicon substrate, an insulation film 2 is deposited, and then a connection hole 3 is provided on the first n-type diffusion layer 5. Then, a polycrystalline silicon 7 with recessed and projecting parts is deposited on the first n-type diffusion layer 5 and then the recessed and projecting parts are formed on the first n-type diffusion layer by performing etching simultaneously on the polycrystalline silicon 7 and one portion of the first n-type diffusion layer 5. Further, an ion 9 such as arsenic ion is ion-implanted to a substrate at a proper angle, thus enabling the second n-type diffusion layer 8 to be formed. After this, a metal wiring layer 4 is formed by the sputtering method etc. By forming recessed and projecting parts on a surface of the diffusion layer, a contact area between the diffusion layer and the metal wiring layer is increased and the contact resistance can be reduced. Also, by forming the second n-type diffusion layer, breakdown of a junction due to thinning of the first n-type diffusion layer can be prevented.

9. 发明专利

JPH0444470B2 失效
公开(公告)号：JPH0444470B2
公开(公告)日：1992-07-21
申请号：JP12280283
申请日：1983-07-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OOTA YOSHIO , CHIKAMURA TAKAO , MYATA YUTAKA , YANO KOSAKU , FUJIWARA SHINJI
IPC分类号： H01L27/146 , H04N5/335 , H04N5/341 , H04N5/359 , H04N5/369 , H04N5/3728

10. 发明专利

JPH0338753B2 失效
公开(公告)号：JPH0338753B2
公开(公告)日：1991-06-11
申请号：JP9672282
申请日：1982-06-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YANO KOSAKU , MYATA YUTAKA , OOTA YOSHIO , CHIKAMURA TAKAO , FUJIWARA SHINJI
IPC分类号： H01L27/14 , H01L27/146 , H01L31/10

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