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1. 发明专利

JPS59141848A Data pass control circuit 失效
标题翻译：数据通道控制电路
公开(公告)号：JPS59141848A
公开(公告)日：1984-08-14
申请号：JP1559683
申请日：1983-02-01
申请人： Matsushita Electric Ind Co Ltd
发明人： OONO KENZOU , MASUDA MICHINORI , WATANABE YOSHINORI
IPC分类号： H04J3/24 , H04L12/42
CPC分类号： H04L12/42
摘要： PURPOSE:To obtain a data pass control system with high efficiency and high reliability by transmitting only the data including a data packet or the parts before and after said data packet to the next station when the data is transmitted over the stations in a loop or bus form cascade connection. CONSTITUTION:If a false header X emerges before a real data packet for the output of a shift registe 20; a decoder 21 outputs a wrong header detection pulse N'2 in the form of a signal DSDT. Then a flip-flop 23 is set at a high level. Meanwhile, the pass data passed through an AND gate 32 is supplied to a memory 25. However, a pulse N2 is outputted when the header of a real data packet is supplied. An RS flip-flop 23 is kept at a high level, and the signal DSDT or FTDT is applied with OR through an OR gate 31 and is supplied to a clear terminal of the memory 25. Thus the data is cleared. In such a way, only the real data packet passes through stations.
摘要翻译：目的：通过在循环或总线上通过站点传输数据，通过仅将包含数据分组的数据或所述数据分组之前和之后的部分发送到下一个站，来获得高效率和高可靠性的数据传输控制系统形成级联连接。构成：如果错误标题X出现在移位寄存器20的输出的真实数据包之前; 解码器21以信号DSDT的形式输出错误的标题检测脉冲N'2。然后将触发器23设置在高电平。同时，通过与门32通过的通过数据被提供给存储器25.然而，当提供实数据包的头部时，输出脉冲N2。 RS触发器23保持在高电平，并且信号DSDT或FTDT通过或门31施加OR，并被提供给存储器25的清除端。因此数据被清除。以这种方式，只有真实的数据包通过站。

2. 发明专利

JPS5679546A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5679546A
公开(公告)日：1981-06-30
申请号：JP15712979
申请日：1979-12-03
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OONO KENZOU , ASABE TSUTOMU
IPC分类号： H04L7/00 , H04L7/02 , H04L25/49
摘要： PURPOSE:To make easy the pickup of bit synchronism and to increase the reliability of data transmission without step-out, by providing the data conversion system suitable for the transmission line encoding between the data source and the transmission encoder and increasing the timing component shown in the transmission signal. CONSTITUTION:In the transmission section as shown in figure, the data is synchronized with the clock CL from a control circuit 13 and is input to a work discrimination circuit 8 in parallel in word unit. It is discriminated at this circuit 8 that all the bits of the inputted word are neither logic ''1'' or ''0'', and the control signals P1-P3 are outputted according to it. This signal is counting circuits 9, 10 and the countered outputs S1 and S2 are fed to the control circuit 13. This control circuit 13 transmits the control signal to shown the conversion method for the conversion circuit 14 according to the control signals from the counting circuits 9, 10. Thus, when the transmission line code is NRZ code, it is inhibited that the same is consecutive over a constant bit and when NRZi code, code conversion is made so that a number of data of logic ''1'' are produced

3. 发明专利

JPS564103A PHOTO SWITCHING ELEMENT 失效
公开(公告)号：JPS564103A
公开(公告)日：1981-01-17
申请号：JP7943579
申请日：1979-06-22
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ASABE TSUTOMU , OONO KENZOU , YOSHINO HIROKAZU
IPC分类号： G02B26/08 , G02B6/35
摘要： PURPOSE:To make possible (n) input and (n) output with simple constitution by providing the connecting body which connects the slots of the plate bodies on the input side and output side to one to one and is rotatable between both plate bodies which are provided with n-number of slots at an equal spacing on the circumference. CONSTITUTION:A switching element 10 is constituted by two sheets of discs 10P, 10S provided with n-number of slits at an equal spacing on the circumference and n-pieces of fibers 10X connecting between the respective slots. The input signals of n-number may be converted one to one, to the output signals of n-number through opposing of the slits of the input side disc 10P and the slots of the output side disc 10S. The n-circuits on the input side are bundled as a cylindrical body 20 and the n-circuits on the output side are bundled as a cylindrical body 30, and these are arrayed on the circumferences of the same shape in opposition to the respective discs 10p, 10s. Here, the switching element 10 is rotatable about the central axis Z1 of the circumference and the correspondence of the input and output lines may be changed by its turning operation, thus the (n) input and (n) output are made possible by the simple constitution.

4. 发明专利

JPS55162629A DIFFERENTIAL CODING METHOD 失效
公开(公告)号：JPS55162629A
公开(公告)日：1980-12-18
申请号：JP7172379
申请日：1979-06-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OONO KENZOU , ASABE TSUTOMU , YOSHINO HIROKAZU
IPC分类号： H03M3/04 , H04B14/06 , H04N19/50
摘要： PURPOSE:To detect the transit of mode and to send the specific code with the significance to the reception side, by dividing the value of the prediction error signal into two modes for the separate quantization and code conversion and monitoring the value of the prediction error signal at the transmission side. CONSTITUTION:The signal from the input terminal 15 is digitized at the A/D converter 16 at the transmission side, and the difference between the digital signal and the output of the prediction circuit predicting the digital signal (prediction signal) is generated at the subtraction circuit 17 (prediction error signal), and the prediction error signal is input to the prediction error detection circuit 18 and the quantizing circuit 19. The quantizing circuit 19 quantizes the prediction error signal, the output is input to the code conversion circuit 20, and it is fed to the reception side after code conversion. At the reception side, the reception code signal is input to the code inversion circuit 24 and the code detection circuit 25. The code inversion circuit 24 generates the quantized signal at transmission and the output signal is obtained with D/A conversion based on it.

5. 发明专利

JPS5531383A TERMINAL DATA COLLECTION METHOD 失效
公开(公告)号：JPS5531383A
公开(公告)日：1980-03-05
申请号：JP10528678
申请日：1978-08-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ASABE TSUTOMU , OONO KENZOU , YOSHINO HIROKAZU
IPC分类号： G06F3/02 , H04N7/16 , H04N7/173
摘要： PURPOSE:To make the collection device of the center simple constitution by transmitting the timing synchronizing signal for sending out data from the center to the terminal and performing data transmission in accordance with the aforesaid synchronizing signal on the part of the terminal. CONSTITUTION:The data signals from the terminal keyboard equipments 11a-11g are stored in the latch circuit as information of ''g'' bits through the level conversion circuit 13. In this case, g means the number of bits of 1 group of the terminal keyboard equipment. The data of g bits mentioned above are stored in the buffer unit 17 after the control information of k+1 bits has been applied. These data are read in the processing unit 19, and subsequently are transmitted to the control unit 20 after judging a character and checking an error concerning the data of each terminal. The terminal keyboard is divided into groups whose number is n, and g bits of the keyboard data are loaded simultaneously to 1 group each. The synchronizing signal generation circuit 18 generates the timing signal of data transmission and loading for each key group, and the synchronizing signal of 1 group to each keyboard equipment is transmitted through the level conversion circuits 13, 14, as the same signal.

6. 发明专利

JPS5525143A DATA TRANSFER CONTROLLER 失效
公开(公告)号：JPS5525143A
公开(公告)日：1980-02-22
申请号：JP9791278
申请日：1978-08-10
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ASABE TSUTOMU , OONO KENZOU , YOSHINO HIROKAZU
IPC分类号： G06F11/00 , G06F3/00 , G06F13/00
摘要： PURPOSE:To reduce errors due to a change in enviromental condition by controlling the pulse width, pulse period and guard time of a control signal for data transfer by using a counter circuit and then by setting them accurately by a gate circuit. CONSTITUTION:At the time of the transfer of a great volume of data between computers at a constant interval of time, clock generator 4 composed of a crystal oscillator and counter generates transfer clocks of period T. This clock sets FF5, whose output is outputted as clock signal (a) to either computer via pulse generating circuit 6 and level converter circuit 3. Strobe signal C from the computer is applied via level converter circuit 8 to FF9, whose output allows counter 10 to count clock pulses CK of generator 4, and gate circuits 11 and 13 are controlled by the output of counter 10 to set the timing of data the other computer sends and that for resetting FFs 5 and 9, thereby reducing errors caused by a change in enviromental condition.

7. 发明专利

JPS54115035A DATA CONCENTARTION UNIT 失效
公开(公告)号：JPS54115035A
公开(公告)日：1979-09-07
申请号：JP2297178
申请日：1978-02-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ASABE TSUTOMU , OONO KENZOU , YOSHINO HIROKAZU
IPC分类号： G06F17/40
摘要： PURPOSE:To reduce the number of receivers in the center, by taking a plurality of terminal units into one group at a bundle, in bidirectional CATV unit and constituting that the data receiver is provided every group. CONSTITUTION:The terminal keyboard units 1-1, 1-2...1-g, in total g sets, are taken as one group and they are connected to the multiplexer 2-1. The umltiplexer 2-1 scanns g sets of keyboards in a given time distance T and performs fetching and serial parallel conversion for the request data from the receiver 3-1 in the time slot distance of T/g, and the output is stored in the buffer unit 4-1. Next, this data is scanned with the nultiplexer 5 and inputted to the contol section 6. If number of terminals is many, the occurrence rate of data is comparatively smaller, and if the delivery speed is low, as bidirectional CATV terminal data, thus the number of receivers in the center can be reduced to 1/g, allowing to perform very small and economical system constitution.

8. 发明专利

JPS5346218A STILL PICTURE TRANSMITTER 失效
公开(公告)号：JPS5346218A
公开(公告)日：1978-04-25
申请号：JP12154976
申请日：1976-10-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YOSHINO HIROKAZU , ASABE TSUTOMU , OONO KENZOU
IPC分类号： H04N5/78 , H04N7/08 , H04N7/173
摘要： PURPOSE:To shorten the average access time, by reading out the still picture for several frames at a bundle to the request of the still picture from the terminals thru using the micro fish searching unit of low speed access, and by sequentially recording this to the frame memory.

9. 发明专利

JPS5345915A INFORMATION TRANSMISSION*RECEIVING UNIT 失效
公开(公告)号：JPS5345915A
公开(公告)日：1978-04-25
申请号：JP12086076
申请日：1976-10-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OONO KENZOU , YOSHINO HIROKAZU , ASABE TSUTOMU
IPC分类号： H04L29/02 , H04L7/04 , H04L7/08
摘要： PURPOSE:Information is divided into blocks consisting of plural bits, and a synchronizing signal is added before the information block to transmit information, so that erroneous operation can be prevented even if the same signal as the synchronizing signal is present in the information block.

10. 发明专利

JPS59204342A Multiple time slot assigning method in loop transmission system 失效
标题翻译：环路传输系统中的多个时间段分配方法
公开(公告)号：JPS59204342A
公开(公告)日：1984-11-19
申请号：JP7850083
申请日：1983-05-04
申请人： Matsushita Electric Ind Co Ltd
发明人： WATANABE YOSHINORI , OONO KENZOU
IPC分类号： H04L5/22 , H04L12/42
CPC分类号： H04L12/42
摘要： PURPOSE:To shorten a circuit connection time by retrieving in a time slot control table on dentritic basis and finding a free time slot speedily. CONSTITUTION:A remote station for data transmission and reception among RSs 2-5 which is called by a terminal sends out a circuit connection request packet to a center station CS1, which decodes the packet to judges the speed of a circuit requested to be used. When a 64 Kbps circuit is requested, the CS1 searches for an SL disable flag to find a G slot that the 64 Kbps circuit can uses, and then searches for the SL flag in the G slot to obtain the address of the time slot to be used; and the originating and terminating RSs among RSs 2-5 are informed of that to report the setting of the circuit.
摘要翻译：目的：缩短电路连接时间，通过在时隙控制表中基于牙质检索，快速查找空闲时隙。构成：由终端呼叫的RS5之间的数据发送和接收的远程站向中心站CS1发送电路连接请求分组，中央站CS1解码分组以判断请求使用的电路的速度。当请求64Kbps电路时，CS1搜索SL禁止标志以找到64Kbps电路可以使用的G时隙，然后在G时隙中搜索SL标志以获得时隙的地址用过的; 并且通知RS 2-5中的起始和终止RS以报告电路的设置。

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