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1. 发明专利

JP2005018798A Lsi design method 有权
标题翻译： LSI设计方法
公开(公告)号：JP2005018798A
公开(公告)日：2005-01-20
申请号：JP2004217789
申请日：2004-07-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SHIOMI KENTARO , MOTOHARA AKIRA , FUJIWARA MUTSUMI , YOKOYAMA TOSHIYUKI , FUJIMURA KATSUYA
IPC分类号： G06F21/24 , G06F12/14 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To further enhance the secret property of circuit design data by adapting an encrypting processing in design of LSI. SOLUTION: In encrypting processing SA, circuit design data 11 which need secrecy are encrypted to generate encrypted design data 12 and a key 13 for releasing the encryption. The encrypted design data 12 are provided to a user who executes design/verification processing SB, and the key 12 is also provided together as occasion demands. In the design/verification processing SB, the encrypted design data 12 are variously processed while keeping the secrecy of the content of the original circuit design data. In decoding processing SC, encrypted design data 14 after execution of design/verification processing S2 are decoded to generate the original circuit design data 15. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过适应LSI设计中的加密处理来进一步提高电路设计数据的秘密性。解决方案：在加密处理SA中，需要保密的电路设计数据11被加密以产生用于释放加密的加密设计数据12和密钥13。加密设计数据12被提供给执行设计/验证处理SB的用户，并且密钥12也根据需要一起提供。在设计/验证处理SB中，加密设计数据12被不同地处理，同时保持原始电路设计数据的内容的保密性。在解码处理SC中，对设计/验证处理S2执行之后的加密设计数据14进行解码，生成原始电路设计数据15.（C）2005，JPO＆NCIPI

2. 发明专利

JP2001338010A METHOD FOR DESIGNING INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001338010A
公开(公告)日：2001-12-07
申请号：JP2000154707
申请日：2000-05-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TAKAHASHI MIWAKA , MOTOHARA AKIRA , OGAWA OSAMU
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To realize design for achieving power reduction at the beginning of design by applying a transaction analyzing technique to the power consumption analysis of an LSI. SOLUTION: Architecture design(AD), architecture floor plan (AF), and transaction analysis(TA) are performed by steps ST11, 12, and 13. Then, floor plan (TF) based on a transaction analytic result is performed in an ST14. Area estimation (CE) for connection with functioning parts is performed in an ST 15, and the floor plan (CF) of an area base is performed in an ST16, and area optimization (CO) is performed in an ST17, and the confirmation of whether or not area specifications are fulfilled is performed in an ST18. Power consumption estimation(PE) is performed in an ST19, and the confirmation of whether or not power consumption specifications (PR) are fulfilled is performed in an ST20. At the time of realizing power reduction in parallelization, power reduction design (PD) from an ST21 to an ST22 is performed. After the power consumption specifications are fulfilled, power source wiring and floor plan is performed in an ST23.

3. 发明专利

JPH07244679A FUNCTION DESIGN ASSITING DEVICE AND FUNCTION DESIGNING METHOD 失效
公开(公告)号：JPH07244679A
公开(公告)日：1995-09-19
申请号：JP3212894
申请日：1994-03-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MOTOHARA AKIRA
IPC分类号： G06F17/50
摘要： PURPOSE:To provide the function design assisting device which can easily know the concrete contents of test facilitation design by confirming test easiness on a function diagram representing the operation function of a logic circuit with a figure, a table, or characters. CONSTITUTION:A function diagram editor part 4 generates the function diagram on the basis of information which is inputted from an input device 1. A function diagram check part 5 tests whether or not the function diagram has contradiction and displays the test result on a display device 2. Here, when the function diagram has the contradiction, the function diagram editor part 4 corrects the function diagram and then the function diagram check part 5 tests whether or not the function diagram has contradiction again. Then when the function diagram has no contradiction, a testability check part 6 confirms the easiness of the function diagram and displays the confirmation result on the display device 2. When the test easiness is good, a function description language conversion part 7 generates a function description language from the function diagram.

4. 发明专利

JPH0587885A GENERATION OF INSPECTION SERIES 失效
公开(公告)号：JPH0587885A
公开(公告)日：1993-04-06
申请号：JP25088391
申请日：1991-09-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HOSOKAWA TOSHINORI , MOTOHARA AKIRA , OTA MITSUHO
IPC分类号： G01R31/3183 , G06F11/22 , G06F11/26 , G06F17/50
摘要： PURPOSE:To obtain the high trouble detecting rate by storing the circuit state as prohibition state when the generation of the inspection series of the circuit state fails and obtain the inspection series so as not to accord with the prohibition state when the inspection series for other generacy trouble is generat ed. CONSTITUTION:Since '1' can not be set simultaneously at each D flip-flop (DFF) 407, 408, a prohibition state is memorized when the inspection series of 0 degeneracy trouble in the signal line which communicates to an AND gate 411 can not be generated. When the inspection series of 1 degeneracy trouble 416 is obtained, '0' is allotted to an outside input pin 405, and a trouble 416 is excited, and in order to propagate the result to an outside output pin 406, a DFF 407 and two-input OR gate 413 are desired to be set to '1' so that the gate input 411 free from the trouble signal obtains '1', and if '1' is allotted to the DEF 407, '1' can not be allotted to a DFF 408, because of the prohibition state. Accordingly, '1' is allotted to a DFF 409, and the DFF 497 and 409 are put into '1' circuit state, and '1' is applied to the pin 405, and the trouble 416 is excited, an propagated to the pin 406.

5. 发明专利

JPH04344540A CHECK LIST GENERATION METHOD 失效
公开(公告)号：JPH04344540A
公开(公告)日：1992-12-01
申请号：JP11600491
申请日：1991-05-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OTA MITSUHO , TAKEOKA SADAMI , MOTOHARA AKIRA
IPC分类号： G06F11/22 , G06F17/50
摘要： PURPOSE:To provide a method for compressing the list length while keeping the generated check list as a higher fault detection rate than an objective fault detection rate on the check list generation checking the presence or absence of faults in the logic circuit. CONSTITUTION:In a step 2, the only when the fault detection rate of the check list is not lower than the objective fault detection rate when the check list capable of obtaining sufficient high fault detection rate on a single reduction fault is generated at the time of check list generation 1 checking the presence or absence of the fault in the logic circuit, the expectation pattern with the small number of fault detections is removed from the check lists in order.

6. 发明专利

JPH03129438A INSPECTION INPUT GENERATING METHOD AND EASY INSPECTION DESIGN METHOD 失效
公开(公告)号：JPH03129438A
公开(公告)日：1991-06-03
申请号：JP18000190
申请日：1990-07-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HOSOKAWA TOSHINORI , MOTOHARA AKIRA
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G06F11/22 , G06F17/50
摘要： PURPOSE:To reduce calculation time and and the area of a chip by recognizing a register which makes the generation of inspection input hard in the middle way of generating the inspection input, and replacing the register by a scan register. CONSTITUTION:A scan request times critical value is designated to each register, and the generation of the inspection input which propagates the influence of a fault selected by using algorithm in which known circuit topology is used to the external output pin of a circuit is performed. At such a case, for example, when a value exceeds the limiting value of the number of times of an operation repeating the re-setting of the value to an external input pin to detect one fault, inspection input generating processing for the fault is interrupted, and the number of times of scan request of the register in which the fault can be detected by performing scan is updated. And the register with the critical value exceeding the number of times of scan request is recognized, and the register is replaced by the scan register, and after that, the next processing for the fault is performed on a changed circuit. In such a way, the calculation time and the number of additional hardware can be reduced.

7. 发明专利

JPH02181465A PACKAGING METHOD OF SEMICONDUCTOR CHIP 失效
公开(公告)号：JPH02181465A
公开(公告)日：1990-07-16
申请号：JP171889
申请日：1989-01-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OKAMOTO OSAMU , SAKAMOTO YOSHIKI , YAMAGUCHI SEIJI , MIYOSHI AKIRA , NINOMIYA KAZUKI , MOTOHARA AKIRA
IPC分类号： H01L25/18 , H01L25/04
摘要： PURPOSE:To conduct packaging with high density and to cool a semiconductor chip effectively by vertically fixing the chip previously inspected as a complete nondefective onto a wafer. CONSTITUTION:The fixing section 26 of a semiconductor chip 2 previously inspected as a nondefective is inserted vertically to the fixing section of a wafer 4 on which wirings 30 are executed. Consequently, the pad 24 of the chip 2 is connected to the pad 36 of the wafer 4, and a data is led out to an external device from a pad 32 through the wiring 30. According to the constitution, packaging density onto the wafer chip 4 can be increased while the chip is cooled easily.

8. 发明专利

JP2006332684A Semiconductor device, functional setting method therefor, and its evaluation method therefor 审中-公开
标题翻译：半导体器件，其功能设置方法及其评估方法
公开(公告)号：JP2006332684A
公开(公告)日：2006-12-07
申请号：JP2006174445
申请日：2006-06-23
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： FUJIMURA KATSUYA , YOKOYAMA TOSHIYUKI , SHIOMI KENTARO , MOTOHARA AKIRA
IPC分类号： H01L27/04 , G01R31/317 , H01L21/82 , H01L21/822 , H01L25/04 , H01L25/18
CPC分类号： H01L2924/0002 , H01L2924/15192 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, its evaluation method, and its functional setting method which are structured, by including a plurality of chip IPs on a common semiconductor wiring substrate and which can be suitable for "small variety and mass production".
SOLUTION: Various IP group can be mounted as a chip IP on a silicon wiring substrate 10. The silicon wiring substrate 10 comprises a silicon substrate 11, a ground plane 12, a wiring layer, such as a first wiring layer 13 and a second wiring layer 14, and a pad 15. It is structured, having an IP (chip IP) mounted on the pad 15 by pasting/Attempt is made to make the semiconductor device to be general-purpose, by installing as many functions as possible, enabling selection of the necessary functions according to the purpose of use, and the device is made suitable for small variety and mass production by providing means for selecting, switching, and setting the function of each IP.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件及其评估方法及其功能设置方法，其通过在公共半导体布线基板上包括多个芯片IP并且可以适用于“小品种和大量生产”。解决方案：可以将各种IP组作为芯片IP安装在硅布线基板10上。硅布线基板10包括硅基板11，接地平面12，布线层，例如第一布线层13和第二布线层14和焊盘15.它被构造成具有通过粘贴安装在焊盘15上的IP（芯片IP），尝试通过安装多个功能来使半导体器件成为通用的可以根据使用目的选择必要的功能，并且通过提供用于选择，切换和设置每个IP的功能的装置，使该装置适合于小型品种和批量生产。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2002118229A SEMICONDUCTOR DEVICE, METHOD FOR SETTING FUNCTION OF THE SEMICONDUCTOR DEVICE, AND METHOD FOR EVALUATING THE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002118229A
公开(公告)日：2002-04-19
申请号：JP2000305653
申请日：2000-10-05
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： FUJIMURA KATSUYA , YOKOYAMA TOSHIYUKI , SHIOMI KENTARO , MOTOHARA AKIRA
IPC分类号： G01R31/28 , G06F15/78 , G06F17/50 , H01L21/82 , H01L21/822 , H01L23/538 , H01L23/544 , H01L27/04 , H04L9/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is configured by mounting a plurality of chips IP onto a common semiconductor wiring board, and is applicable to a small variety mass production, and to provide a method for evaluating the semiconductor device and a method for setting the function of the semiconductor device. SOLUTION: On a silicon wiring board 10, each kind of IP group can be mounted as a chip IP. The silicon wiring board 10 has a silicon substrate 11, a ground plane 12, a wiring layer such as first and second wiring layers 13 and 14, and a pad 15. Then, the IP (IP chip) is laminated for mounting onto the pad 15. A means for selecting, switching, and setting the function of each IP is provided, thus providing as many functions as possible for achieving versatility in the semiconductor device, at the same time, selecting functions required according to the purposes of use, and adapting to a small variety mass production.

10. 发明专利

JP2547281B2 失效
公开(公告)号：JP2547281B2
公开(公告)日：1996-10-23
申请号：JP2086891
申请日：1991-02-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TAKEOKA SADAMI , MOTOHARA AKIRA
IPC分类号： G01R31/26 , G01R31/28 , G06F11/00 , H01L21/66 , H01L21/822 , H01L27/04

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