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1. 发明专利

JP2008083189A Phase shift mask and method for manufacturing light condensing element 审中-公开
标题翻译：相变膜掩模和制造光聚光元件的方法
公开(公告)号：JP2008083189A
公开(公告)日：2008-04-10
申请号：JP2006260770
申请日：2006-09-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHII MOTONORI , ONOZAWA KAZUTOSHI , TOSHIKIYO KIMIAKI , MATSUNO TOSHINOBU , YOKO TAKANORI
IPC分类号： G03F1/29 , G03F1/68
CPC分类号： G03F7/0005 , G03F1/30
摘要： PROBLEM TO BE SOLVED: To provide a phase shift mask for improving the accuracy of a fine structure in a semiconductor device having a concentric pattern. SOLUTION: The phase shift mask for manufacturing a semiconductor element comprises concentrically disposed light shielding portions 101b, 101a2, 101a1, a light transmitting portion 102, a phase shift portion 103 and an auxiliary pattern portion 104, wherein the width of the auxiliary pattern portion 104 in a radial direction is smaller than both of the width of the light transmitting portion 102 in the radial direction and the width of the phase shift portion 103 in the radial direction. The phase of exposure light passing through the auxiliary pattern portion 104 may be an inverted phase to the phase of exposure light passing through the light transmitting portion 102 or the phase shift portion 103 close to the auxiliary pattern portion 104. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于提高具有同心图案的半导体器件中的精细结构精度的相移掩模。解决方案：用于制造半导体元件的相移掩模包括同心设置的遮光部分101b，101a2,101a1，光透射部分102，相移部分103和辅助图案部分104，其中辅助径向方向上的图案部分104小于透光部分102在径向上的宽度和相移部分103在径向方向上的宽度。通过辅助图案部分104的曝光光的相位可以是与通过透光部分102或相移部分103接近辅助图案部分104的曝光光的相位相反的相位。版权所有（ C）2008，JPO＆INPIT

2. 发明专利

JPH0669222A HETERO-JUNCTION BIPOLAR TRANSISTOR AND ITS PRODUCTION 失效
公开(公告)号：JPH0669222A
公开(公告)日：1994-03-11
申请号：JP21764192
申请日：1992-08-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUNO TOSHINOBU , NAKAGAWA ATSUSHI , HIROSE TAKASHI , INOUE KAORU
IPC分类号： H01L29/205 , H01L21/331 , H01L29/10 , H01L29/73 , H01L29/737
摘要： PURPOSE:To increase the field intensity in a base layer inner electric field by giving a gradient impurity concentration to the base layer. CONSTITUTION:A base layer 4 is constituted of 100nm thick Inx(AlyGa1-y)1-xAs(0

3. 发明专利

JPH05304163A 失效
公开(公告)号：JPH05304163A
公开(公告)日：1993-11-16
申请号：JP10965592
申请日：1992-04-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROSE TAKASHI , MATSUNO TOSHINOBU , INOUE KAORU
IPC分类号： H01L29/205 , H01L21/331 , H01L29/73 , H01L29/737
摘要： PURPOSE:To obtain high-current gains even when a high current region and element size are fined regarding a hetero-junction bipolar transistor having collector-up structure and manufacture thereof. CONSTITUTION:A multilayer film structure including a first emitter layer 23 consisting of n-type Al0.3Ga0.7As, a second emitter layer 24 made up of N-type Al0.6a0.4As and a base layer 25 composed of high-concentration P-type GaAs and an external base layer 31 brought into contact with the second emitter layer 24 and not brought into contact with the first emitter layer 23 and containing P-type Al0.6Ga0.4As and a high resistance layer 30 just under the external base layer 31 are formed onto a substrate 21.

4. 发明专利

JPH0346241A SEMICONDUCTOR HETEROSTRUCTURE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0346241A
公开(公告)日：1991-02-27
申请号：JP18057489
申请日：1989-07-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOUE KAORU , JIEI SHII ARUMAN , MATSUNO TOSHINOBU
IPC分类号： H01L29/205 , H01L21/203 , H01L21/337 , H01L21/338 , H01L29/778 , H01L29/808 , H01L29/812
摘要： PURPOSE:To make it possible to form an active layer while the good crystal quality of the active layer is held by a method wherein the compositional ratio of InAs of a buffer layer is changed almost linearly to the thickness direction between the side of a GaAs substrate and the active layer and the rate of change of the compositional ratio is set as 1.5X10 /nm or lower. CONSTITUTION:The composition (X) of InAs of a non-doped InxGa1-xAs buffer layer 12 is set as 0 on the side of a semi-insulative GaAs substrate 10, is increased linearly toward the side of the surface, is set as 0.53 in the interface between the layer 12 and a non-doped In0.52Al0.48As barrier layer 13, is set as a composition, which can make a lattice matching with each layer 13 to 16 located on the side of the surface from the layer 13, and the rate of change of the composition (x) is set as 1.5X10 /nm or lower. Because of this, the crystallizability of an active layer formed on the buffer layer 12 is remarkedly improved and the crystal quality of the active layer can be favorably held. Thereby, while the InGaAs and InAlAs layers, whose grating constants are greatly different from one another, are grown, the active layer can be formed so as to have a superior crystal quality.

5. 发明专利

JPH02254731A HETERO-JUNCTION TYPE FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH02254731A
公开(公告)日：1990-10-15
申请号：JP7756589
申请日：1989-03-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOUE KAORU , JIIN KURISUTOFU ARUMAN , MATSUNO TOSHINOBU
IPC分类号： H01L29/812 , H01L21/20 , H01L21/338 , H01L29/778
摘要： PURPOSE:To enable a novel hetero-junction structure lightening the restriction on the lattice alignment to be manufactured by a method wherein InGaAs, InAlAs in larger lattice constant than that of an InP substrate are used in the region in film thickness exceeding the film thickness. CONSTITUTION:A non-doted InyAl1-yAs layer 11 in larger lattice constant than that of an InP substrate 1, another non-doped InxGa1-xAs layer 12, the other non-doped InyAl1-yAs thin film 13 and an N type InyAl1-yAs layer 14 respectively in the same lattice constant as that of the the said layer 11 are successively formed on the semiinsulating InP substrate 1. Then, the whole thickness of the layers formed on the InP substrate 1 is set up thicker than the film thickness determined by the difference from the lattice constant of the semiinsulating InP substrate 1. Through these procedures, the restriction on the crystal deposition such as the lattice alignment with the InP substrate 1 can be lightened so as to attain the simplification, the mass production and the price cut down of the crystal deposition process.

6. 发明专利

JPH01145871A HETEROJUNCTION TYPE FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH01145871A
公开(公告)日：1989-06-07
申请号：JP30506887
申请日：1987-12-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOUE KAORU , MATSUNO TOSHINOBU
IPC分类号： H01L29/201 , H01L21/338 , H01L29/778 , H01L29/80 , H01L29/812
摘要： PURPOSE:To improve reproducibility in manufacturing a hetero structure and to improve the yield rate in manufacturing, by replacing an N-type GaAs layer and a non-doped GaAs layer with non-doped AlGaAs, an N-type AlGaAs layer and a non-doped AlGaAs layer in a heterojunction FET. CONSTITUTION:On a GaAs buffer layer, a non-doped AlGaAs layer 3 having a thickness of 100Angstrom or less, an N-type AlGaAs layer 4 having a thickness of 50-100Angstrom and a non-doped AlGaAs layer 5 having a thickness of 20Angstrom are sequentially grown, and a first electron feeding layer is formed. An InxGa1-xAs layer 6 having a thickness of 100-200Angstrom , in which the composition ratio of InAs is 0.25 or less, is formed thereon. A non-doped AlGaAs spacer layer 7 having a thickness of 2Angstrom and an N-type AlGaAs layer 8 are formed on the InxGa1-xAs layer 6, and a second electron feeding layer is formed. In this structure, the composition ratio of AlAs in the entire AlGaAs layers is made to be 0.2 or less in order to decrease the concentration of a deep defect called a DX center, which is included in the N-type AlGaAs and to stabilize the characteristics of the FET at low temperature. The typical value of the ratio 0.15 is used.

7. 发明专利

JPH01143271A MANUFACTURE OF HETERO JUNCTION TYPE FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPH01143271A
公开(公告)日：1989-06-05
申请号：JP30070987
申请日：1987-11-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOUE KAORU , MATSUNO TOSHINOBU
IPC分类号： H01L21/20 , H01L21/338 , H01L29/205 , H01L29/778 , H01L29/812
摘要： PURPOSE:To greatly improve the yield of crystal growth by extending the allowable range of a substrate temperature during the growth of a crystal by causing thin AlGaAs to grow without causing an InxGa1-xAs layer 4 to grow directly on a GaAs buffer layer, and thereafter causing the InxGa1-xAs layer to grow. CONSTITUTION:There are formed on a semi-insulating GaAs substrate 1 a non-doped GaAs buffer layer 2 of thickness of 0.3mum-1mum, an AlGaAs layer 3, an InxGa1-xAs layer 4, a non-doped AlGaAs spacer layer 5 with a composition ration of AlAs of 0.2 or less, an N-type GaAs layer 7 in this order. Growth of the InxGa1-xAs layer 4 via the AlGaAs 3 in a range of substrate temperature below 520 deg.C assures electrical characteristics of the product are substantially constant over a wide temperature range of 45-540 deg.C.

8. 发明专利

JP2003174033A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003174033A
公开(公告)日：2003-06-20
申请号：JP2001373696
申请日：2001-12-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SONETAKA SHINICHI , TOYODA YASUYUKI , MATSUNO TOSHINOBU
IPC分类号： H01L29/417 , H01L21/3205 , H01L21/331 , H01L23/52 , H01L29/41 , H01L29/732 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To reliably increase gain in a high-frequency bipolar type transistor. SOLUTION: A second emitter wiring 16 is formed so that the entire surface on a transistor region is covered. In an entire emitter region 3, difference in inductance due to the routing of wiring is eliminated, thus canceling the phase deviation of an RF signal, and hence reliably increasing gain. COPYRIGHT: (C)2003,JPO

9. 发明专利

JPH08316462A METHOD OF GROWING SEMICONDUCTOR CRYSTAL AND DEVICE THEREOF 失效
公开(公告)号：JPH08316462A
公开(公告)日：1996-11-29
申请号：JP11572795
申请日：1995-05-15
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TANABE MITSURU , INOUE KAORU , MATSUNO TOSHINOBU
IPC分类号： H01L29/205 , H01L21/20 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE: To improve the mobility of electrons in the channel layer to be formed by the growth of crystal on a semiconductor layer. CONSTITUTION: After a buffer layer 11, an undoped layer 12 and a semiconductor layer 13 have been successively grown on a GaAs semiconductor substrate 10, an impurity-undoped GaAs channel layer 14 is crystal-grown on the semiconductor layer 13. As the electrons of two-dimensional electron gas are migrate to the opposite side of crystal growth direction and diffused into the semiconductor layer 13 because crystal is grown while electric field is being applied to crystal growth direction, the migration of electrons to the channel layer 14 is lessened, and a defect is not formed on the channel layer 14. Then, after an impurity-doped GaAs cap layer 15 has been formed on the channel layer 14, the cap layer 15 is recess-etched, and a gate electrode 16, a source electrode 17 and a drain electrode 18 are formed.

10. 发明专利

JPH0567771A SEMICONDUCTOR MULTILAYER FILM WAFER AND MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0567771A
公开(公告)日：1993-03-19
申请号：JP22570991
申请日：1991-09-05
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROSE TAKASHI , MATSUNO TOSHINOBU , RIYUUJI AKIRA , INOUE KAORU
IPC分类号： H01L29/205 , H01L21/331 , H01L29/73 , H01L29/737
摘要： PURPOSE:To provide a manufacturing method for a semiconductor multilayer film wafer that has an accurate end point in an etch removal step for an emitter layer, and also for a hetero bipolar transistor with a semiconductor multilayer film wafer. CONSTITUTION:A multilayer film structured region 27 for mounting a hetero junction bipolar transistor and a colorimetric structured region 29 are formed on a GaAs substrate 21. The colorimetric structured region 29 can be discriminated from the multilayer film structured region 27 through the surface color thereof. The colorimetric structured region 29 is formed with a material having a film thickness not less than a distance from the surface of the multilayer film structured region 27 to the base layer and also having an inihibited band width almost equal to that of the base layer.

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