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1. 发明专利

JP2006166519A Switching dc power supply 有权
标题翻译：切换直流电源
公开(公告)号：JP2006166519A
公开(公告)日：2006-06-22
申请号：JP2004350918
申请日：2004-12-03
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAGAWA ATSUSHI , KOMATSU AKIYUKI
IPC分类号： H02M3/28
CPC分类号： Y02B70/16
摘要： PROBLEM TO BE SOLVED: To provide a switching DC power supply comprising a power supply voltage detection circuit having hysteresis in which power consumption through a starting resistor for detecting DC voltage is minimized.
SOLUTION: The switching DC power supply comprises a starting resistor R1 being connected to the DC positive electrode side of a bridge diode D1 for rectifying AC voltage, a capacitor C1 being connected to the other end of the starting resistor R1 through a start control transistor Q1, a starting voltage detection circuit for detecting the starting voltage and the stopping voltage from the voltage value for charging the capacitor C1, and a PWM control circuit IC1 starting operation when the starting voltage detection circuit detects the starting voltage and performing PWM control of a switching transistor Q5 to supply a load with a DC voltage. When the starting voltage detection circuit detects the starting voltage, charging of the capacitor C1 is stopped by interrupting current flow to the starting resistor R1 and when the starting voltage detection circuit detects the stopping voltage, the capacitor C1 is charged by supplying a current to the starting resistor R1 through the transistor Q1.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种包括具有迟滞的电源电压检测电路的开关直流电源，其中通过用于检测直流电压的起动电阻的功耗最小化。解决方案：开关直流电源包括与桥二极管D1的DC正电极侧连接的起动电阻器R1，用于整流交流电压，电容器C1通过启动连接到起动电阻器R1的另一端控制晶体管Q1，用于从用于对电容器C1充电的电压值检测起始电压和停止电压的起动电压检测电路，以及当起动电压检测电路检测到启动电压并执行PWM控制时的PWM控制电路IC1的启动操作的开关晶体管Q5以向DC电压提供负载。当启动电压检测电路检测到启动电压时，通过中断到起动电阻器R1的电流来停止电容器C1的充电，并且当起动电压检测电路检测到停止电压时，电容器C1通过向启动电阻器R1通过晶体管Q1。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JPH05109750A SEMICONDUCTOR DEVICE AND MANUFACTURE OF THE SAME 失效
公开(公告)号：JPH05109750A
公开(公告)日：1993-04-30
申请号：JP26587991
申请日：1991-10-15
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAKAGAWA ATSUSHI
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8228 , H01L27/06 , H01L29/205 , H01L29/73 , H01L29/737
摘要： PURPOSE:To provide a high gain ultra-high speed semiconductor device utilizing a collector top type pnp HBT as a switching transistor and a lateral npnBT as a current injection source and also provide a method of manufacturing semiconductor which has realized high integration density with a simplified process. CONSTITUTION:A semiconductor device is formed by a collector layer 3 of HBT consisting of p type InxAl1-xAs lattice matched with an InP substrate, an emitter layer 5 of HBT and a base layer 4 of HBT consisting of an N type InxGa1-xAs. An external base region and collector region 4a of BT consisting of N type InxGa1-xAs and N type InxAl1-xAs and an emitter region 6 of BT consisting of N type InxAl1-xAs are formed by introduction of a substance which will become an N type impurity. The base of BT and collector of HBT are used in common and are connected to a contact layer 2 consisting of the P type InxGa1-xAs.

3. 发明专利

JPH04287330A HETEROJUNCTION BIPOLAR TRANSISTOR AND ITS INTEGRATION METHOD 失效
公开(公告)号：JPH04287330A
公开(公告)日：1992-10-12
申请号：JP5210591
申请日：1991-03-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAKAGAWA ATSUSHI
IPC分类号： H01L29/205 , H01L21/331 , H01L29/73 , H01L29/737
摘要： PURPOSE:To obtain a heterojunction bipolar transistor capable of both modes operation of an emitter top type and a collector top type and of low consumption power operation using a small ON-voltage, and an integration method capable of improving integration efficiency by a simple process. CONSTITUTION:The title transistor is constituted of the following; a collector layer 3 and an emitter layer 5 composed of P-type InxAl1-xAs lattice-matched with an InP substrate 1, a base layer 4 composed of N-type InxGa1-xAs, a first spacer layer 3a composed of P-type InxGa1-xAs inserted between a base and a collector, and a second spacer layer 5a composed of P-type InxGa1-xAs inserted between the base and an emitter. An outer base region 4a is formed of N-type InxGa1-xAs and N-type InxAl1-xAs by introducing material turning to N-type impurities.

4. 发明专利

JPH04206833A METEROJUNCTION BIPOLAR TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH04206833A
公开(公告)日：1992-07-28
申请号：JP33809390
申请日：1990-11-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INADA MASAKI , NAKAGAWA ATSUSHI , HIROSE TAKASHI , RIYUUJI AKIRA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
摘要： PURPOSE:To remarkably stabilize characteristic of a device, by forming, on substrate material, at least, a highly doped N-type semiconductor layer for forming a first emitter, and a second emitter whose energy band gap is larger than that of the first emitter. CONSTITUTION:Oxide layers 50 and 60 are formed on the side wall of a mesa 30 and on a first emitter 2c, respectively. Said layers are irradiated with As in a high vacuum and heated at 600 deg.C, thereby eliminating the oxide layer on the mesa side surface and exposing the semiconductor surface. Only the oxide layers on the side surface of a first base P -GaAs 4a and on the first emitter layer 2c are selectively eliminated, and an oxide layer 70 on the side surface of a second emitter 3a is left. A second base layer P -Al0.4Ga0.6As 7 is formed by molecular beam epitaxy 40 from above. In this process, the epitaxial growth of the first base 4a and the first emitter 2c becomes nucleus, and the second base layer 7 of P -Al0.4Ga0.6As is formed on also the oxide layer 70. An SiO2 mask 10 is eliminated together with P -Al0.4Ga0.6As 11 stuck on the mask 10, and a collector electrode 8 and a base electrode 9 are formed.

5. 发明专利

JPS63164434A FINE PROCESSING METHOD 失效
公开(公告)号：JPS63164434A
公开(公告)日：1988-07-07
申请号：JP31217786
申请日：1986-12-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROSE TAKASHI , NAKAGAWA ATSUSHI , INADA MASAKI
IPC分类号： H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/80 , H01L29/812
摘要： PURPOSE:To perform a submicron-order fine processing by a self alignment method by forming the length of the eaves of a T-shaped dummy pattern with the film thickness of the side wall film, thereby obtaining a T-shaped dummy pattern which is very good in controllability and is uniform. CONSTITUTION:On a semiconductor substrate 11, a first pattern 12a is formed which consists of a first insulating film and has side walls substantially vertical to the substrate 11. Part of the pattern 12a is exposed, and a second insulating film 15 covering the whole surface of the substrate 11 is formed. After forming a side wall film 17a consisting of a third insulating film 17 on the side walls of exposed part, the insulating film 15 is removed. Hereupon, the length l of the eaves of a fine dummy pattern having a T-shaped cross section is determined by the film thickness of the side wall film 17a. With this, a T-shaped dummy pattern is obtained which is very good in controllability and is uniform, and a submicron-order fine processing by a self alignment method is preformed.

6. 发明专利

JPS63138775A MANUFACTURE OF HETERO JUNCTION BIPOLAR TRANSISTOR 失效
公开(公告)号：JPS63138775A
公开(公告)日：1988-06-10
申请号：JP28632586
申请日：1986-12-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INADA MASAKI , OTA TOSHIMICHI , YANAGIHARA MANABU , NAKAGAWA ATSUSHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/72 , H01L29/737
摘要： PURPOSE:To reduce the contact resistance by increasing a contact area between an electrode and an emitter by a method wherein an emitter and an emitter electrode covering the overall surface of emitter are formed in self alignment using the same mask. CONSTITUTION:A temporary emitter 14 as a mask is etched to expose an outer base region 46. First, an HBT device is formed to form a base electrode 10 and a collector electrode 11 by evaporation, lift off and alloying heat treatment. Second, the temporary emitter 14 is removed by etching process to expose a cap layer 6a by emitter forming a recession 16. Finally, an emitter region 9 is formed by evaporation and lift off process. Through these procedures, overall surface of emitter is covered with the emitter electrode 9 to reduce the contact resistance.

7. 发明专利

JPS6348862A MANUFACTURE OF HETEROJUNCTION BIPOLAR TRANSISTOR 失效
公开(公告)号：JPS6348862A
公开(公告)日：1988-03-01
申请号：JP19329386
申请日：1986-08-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INADA MASAKI , EDA KAZUO , OOTA TOSHIMICHI , NAKAGAWA ATSUSHI
IPC分类号： H01L29/205 , H01L21/331 , H01L29/72 , H01L29/73 , H01L29/737
摘要： PURPOSE:To form a base electrode readily even in a minute external base region in a self-aligning method, by forming the base electrode at a part very close to the junction part of a collector and a base, thereby reducing the resistance of the external base to a remarkably small value. CONSTITUTION:With a temporary collector 13 as a mask, etching is performed to a layer 4 for forming a base by a wet etching method. A collector region comprising a collector 5-a and a cap layer 6-a is formed. Both sides of the region along the extending direction of a stripe are formed in an inverted mesa shape. The entire surface of the upper part of the collector region is covered with a collector electrode 8. The collector electrode has an umbrella shape, i.e., an undercut part, which is formed by etching at the lower part of the collector electrode. A mask is applied on a part other than parts including both ends of the stripe and a base-electrode forming part. Base electrode metal is evaporated and lift-off is performed. Thus a base electrode 9 is formed. In this way, the base electrode 9 is formed at a part very close to the collector electrode at the peripheral part directly beneath the umbrella of the collector electrode metal.

8. 发明专利

JPS62230061A MANUFACTURE OF HETERO STRUCTURE FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPS62230061A
公开(公告)日：1987-10-08
申请号：JP7354986
申请日：1986-03-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAKAGAWA ATSUSHI , HIROSE TAKASHI
IPC分类号： H01L29/812 , H01L21/20 , H01L21/338 , H01L29/778 , H01L29/80
摘要： PURPOSE:To improve the characteristics of a hetero structure field-effect transistor by forming an insulating film on the side of an N type gallium arsenide layer in a channel unit, and forming a gate electrode by resist lifting off to reduce a series resistance between a source electrode and a gate electrode. CONSTITUTION:A gallium arsenide layer 2 (channel layer) which substantially contains no impurity and an N-type aluminum gallium arsenide layer 3 (electron supply layer) which contains N-type impurity are formed. Thereafter, the entire surface is covered with a plasma nitride film 13, which is etched by an RIE unit to form a plasma nitride film 13' on the sidewall of an SiO2 film 11' of a hole 12. A polygallium arsenide layer 2' and a polyaluminum gallium arsenide 3' formed on the film 11' are removed. The entire surface is coated with a resist film, prebaked, patterned, deposited with an aluminum film, and lifted off to form a gate 4. Thus, an interval between a gate electrode and an N-type gallium arsenide layer for a source electrode is determined by the thickness of a second insulating film in a self-aligning manner.

9. 发明专利

JPS60262469A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60262469A
公开(公告)日：1985-12-25
申请号：JP11847784
申请日：1984-06-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAZOE HIROSHI , NAKAGAWA ATSUSHI , HIROSE TAKASHI , YAMASHITA ICHIROU
IPC分类号： H01L21/338 , H01L29/47 , H01L29/812 , H01L29/872
摘要： PURPOSE:To stabilize a semiconductor device against heat treatment at a high temperature while preventing the peeling of a metallic layer by forming the metallic layer shaped from an alloy of Re and W while being brought into contact with the surface of an N type GaAs crystal and forming a Schottky barrier to the surface of the metallic layer. CONSTITUTION:An N type GaAs layer 12 is shaped onto a GaAs substrate 11. First protective layers 13, a metallic layer 14, which forms a Schottky barrier and is shaped from an alloy of Re and W, an ohmic electrode 15 and second protective films 16 are formed onto the layer 12, thus shaping a Schottky barrier type diode. It is preferable that the content of W in the alloy constituting the layer 14 extends over 80atom% or less at that time. Accordingly, the Schottky barrier is stabilized against heat treatment up to approximately 850 deg.C, and the metallic layer is difficult to be peeled remarkably from an N type GaAs crystal.

10. 发明专利

JPS60262463A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60262463A
公开(公告)日：1985-12-25
申请号：JP11851184
申请日：1984-06-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAZOE HIROSHI , HIROSE TAKASHI , NAKAGAWA ATSUSHI , YAMASHITA ICHIROU
IPC分类号： H01L21/338 , H01L29/47 , H01L29/812 , H01L29/872
摘要： PURPOSE:To stabilize a semiconductor device against heat treatment at a high temperature, and to prevent the peeling of a metallic layer by forming the metallic layer shaped from an alloy of Re and Al while being in contact with the surface of an n type GaAs crystal and forming a Schottky barrier to the surface of the metallic layer. CONSTITUTION:An n type GaAs layer 12 is shaped onto a GaAs substrate 11 through epitaxial growth, ion implantation or heat treatment. A metallic layer 14 formed from an alloy of Re and Al for shaping first protective films 13 and Schottky barriers, and ohmic electrode 15 and second protective films 16 are formed onto the layer 12, thus forming a Schottky barrier type diode. It is preferable that the content of Al in the alloy constituting the layer 14 extends over 30atom% or less at that time. Accordingly, the Schottky barrier is stabilized againt heat treatment up to approximately 850 deg.C, and the metallic layer is difficult to be peeled remarkably from the surface of an n type GaAs crystal.

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