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1. 发明专利

JPH0469427B2 失效
公开(公告)号：JPH0469427B2
公开(公告)日：1992-11-06
申请号：JP19564483
申请日：1983-10-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KONDO SHUJI , KITAHIRO ISAMU , TAKAHASHI HIROSHI , HIRAI MINORU
IPC分类号： H01L21/60

2. 发明专利

JPS6169141A Film carrier mounting 失效
标题翻译：电影载体安装
公开(公告)号：JPS6169141A
公开(公告)日：1986-04-09
申请号：JP19130184
申请日：1984-09-12
申请人： Matsushita Electric Ind Co Ltd
发明人： KONDO SHUJI , HIRAI MINORU
IPC分类号： H01L21/603 , H01L21/60
CPC分类号： H01L24/50 , H01L24/86 , H01L2924/01015 , H01L2924/01082 , H01L2924/10157
摘要： PURPOSE:To eliminate the failure such as edge touch and to contrive the high-density mounting by a method wherein the second diffusion layers, which are provided in the regions of the first diffusion layers, are formed in such a way as to reach the end edge of the substrate and the point parts of the inner leads of the film carriers are respectively junctioned by pressure-welding to the electrode metals for connection. CONSTITUTION:Insular N type diffusion layers 15, which are formed in the regions of P type diffusion layers 10, are respectively formed in advance at parts of the peripheral end edge part of the chip, where are positions to correspond to electrode metals 17 for connection, the inner leads 20 of film carriers 10 are respectively disposed pressing on the N type diffusion layers 15 and the point parts thereof are respectively functioned by pressure-welding to the electrode metals 17 for connection. Even though the inner leads 20 come into contact to the insular N type diffusion layers 15, the inner leads 20 have a guard function to a substrate 9 by the existence of the N type diffusion layers 15 and the P type diffusion layers 10 regardless of the polarity of the inner leads 20 and even when edge touches are generated by the plural inner leads 20, the short-circuit between the leads and the substrate is prevented as the N type diffusion layers 15 are isolatedly independent. By this way, the failure such edge touch, which is generated by the contact of the inner leads and the peripheral end edge part of the semiconductor element chip, can be eliminated.
摘要翻译：目的：为了消除诸如边缘触摸的故障，并且通过其中设置在第一扩散层的区域中的第二扩散层以达到最终的方式形成的方法来设计高密度安装基板的边缘和薄膜载体的内部引线的点部分分别通过压焊连接到用于连接的电极金属。构成：在P +型扩散层10的区域中形成的岛状N +型扩散层15分别预先形成在芯片的外周端部边缘部分的部分，其位置对应对于用于连接的电极金属17，膜载体10的内引线20分别设置在N +型扩散层15上，并且其点部分别通过对用于连接的电极金属17进行压焊而起作用。即使内部引线20与岛状N +型扩散层15接触，内部引线20由于存在N +型扩散层15而对衬底9具有保护功能， +>型扩散层10，而不管内引线20的极性如何，即使当多个内引线20产生边缘接触时，也可以防止引线与基板之间的短路作为N +型扩散层 15是孤立独立的。由此，可以消除由内部引线与半导体元件芯片的周边端部接触产生的边缘触摸的破坏。

3. 发明专利

JPS60206035A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60206035A
公开(公告)日：1985-10-17
申请号：JP5946884
申请日：1984-03-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIRAI MINORU , HATADA KENZOU
IPC分类号： H01L21/60
摘要： PURPOSE:To prevent the thermal deformation of a connector by decreasing the heating temperature by a method wherein a metallic projection at the tip of a lead is made to abut against an electrode provided on the surface of a semiconductor element, and at the time of heating adhesion by pressing with a bonding tool, the pressure is divided into two steps. CONSTITUTION:The semiconductor element 4 is placed on a stage 6, and the Au projections 3 at the tips of a lead group 2 adhered under connectors 1 are made to abut against a plurality of Al electrodes 5 provided on the surface of the element 4. Next, the electrodes 5 and the projections 3 are brought into thermal fusion while they are pressed on heating by pressing the bonding tool 7 above the projections 3. At this time, the pressing is divided into two steps: first heating under the condition of a degree that these barely come to contact, and next heating under a normal pressure after the temperature of a junction reaches the alloying temperature. This manner makes it sufficient that impressing time for the second pressure is 0.1-0.5sec, and that the heating temperature is about 400 deg.C; accordingly, thermal deformation or pitch deviation does not generate in the connectors 1.

4. 发明专利

JPH0462458B2 失效
公开(公告)号：JPH0462458B2
公开(公告)日：1992-10-06
申请号：JP6099784
申请日：1984-03-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIRAI MINORU
IPC分类号： H01L21/60

5. 发明专利

JPS6091656A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6091656A
公开(公告)日：1985-05-23
申请号：JP19936983
申请日：1983-10-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HATADA KENZOU , HIRAI MINORU
IPC分类号： H01L21/60
摘要： PURPOSE:To transfer and join a metallic projection into an electrode leading-out region efficiently and positively by forming an organic thin-film for bonding on the electrode leading-out regin in a semiconductor element or the metallic projection formed on a substrate. CONSTITUTION:Electrode leading-out regions 3 in Al are formed on an Si substrate 2 to which an element 1 is shaped, a thin-film 4 consisting of polyimide group resin, etc. having adhesive properties more or less at the normal temperature or at several 100 deg.C is applied, and windows 5 for pushing in protruding electrodes are formed. Metallic projections 8 are formed on a glass plate 7 through Pt or Mo films, which have excellent plating properties and can be peeled and transferred easily. The element 1 is sucked and fixed to a tool 9, and the metallic projections corresponding to the electrode leading-out regions 3 are positioned and pressed 10, and transfered and joined on the regions 3 through the resin film 4. The temperature of the tool is kept properly, and the metallic projections can be transferred and joined on the leading-out regions efficiently and positively under pressure by low pressure.

6. 发明专利

JPS59205747A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59205747A
公开(公告)日：1984-11-21
申请号：JP8031183
申请日：1983-05-09
申请人： Matsushita Electric Ind Co Ltd
发明人： KONDOU SHIYUUJI , HIRAI MINORU , HATADA KENZOU
IPC分类号： H01L25/00 , H01L21/3205 , H01L23/52 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00
CPC分类号： H01L25/0657 , H01L23/5385 , H01L2224/04105 , H01L2224/20 , H01L2224/211 , H01L2225/06524 , H01L2225/06551 , H01L2225/06579 , H01L2924/07802 , H01L2924/09701 , H01L2924/00 , H01L2924/00012
摘要： PURPOSE:To obtain a device having three-dimensional mounting structure while mutually connecting semiconductor elements easily by loading the semiconductor element on a substrate, mounting an electrode terminal while one end is exposed to the edge section of the circumferential wall of the element, bonding a large number of the substrates with a heat-resisting resin and mutually connecting the exposed electrode terminals. CONSTITUTION:A semiconductor element 17 is loaded on an insulating substrate 22, the edge section of the circumferential wall of the element is surrounded by a heat-resisting resin substrate 19, a side surface thereof has an electrode conductive layer 12 and the surface thereof an electrode conductive layer 20, and the projecting section 20' of the conductive layer 20 is connected to a projecting electrode 18 for the element 17. A plurality of the substrates 22 manufactured in this manner are superposed on a ceramic and glass epoxy resin substrate 23 through spacers 24 in small width, an upper surface is coated with a base body 25, and the substrate 23 and the cover body 25 are clamped by a holding frame body 26 and fixed temporarily. Space formed by the spacers 24 is filled with an insulating adhesive resin 27 such as epoxy and the resin is cured, and the electrode conductive layers 21 exposed to the side surfaces are connected with each other, thus manufacturing a device having three-dimensional structure.
摘要翻译：目的：为了获得具有三维安装结构的装置，同时通过将半导体元件加载在基板上而容易地连接半导体元件，在将一端暴露于元件的周壁的边缘部分的同时安装电极端子，大量的具有耐热树脂的基板并且相互连接暴露的电极端子。构成：将半导体元件17装载在绝缘基板22上，元件周壁的边缘部分被耐热树脂基板19包围，其侧面具有电极导电层12，其表面为电极导电层20和导体层20的突出部分20'连接到用于元件17的突出电极18上。以这种方式制造的多个基板22被叠置在陶瓷和玻璃环氧树脂基板23上间隔物24的宽度小，上表面涂有基体25，基板23和盖体25被保持框体26夹紧并暂时固定。由间隔物24形成的空间填充有诸如环氧树脂的绝缘粘合剂树脂27，并且树脂固化，并且暴露于侧表面的电极导电层21彼此连接，从而制造具有三维结构的装置。

7. 发明专利

JPS58220434A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS58220434A
公开(公告)日：1983-12-22
申请号：JP10426782
申请日：1982-06-16
申请人： Matsushita Electric Ind Co Ltd
发明人： HIRAI MINORU
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L24/32 , H01L24/73 , H01L2224/05554 , H01L2224/27013 , H01L2224/29007 , H01L2224/32014 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/49 , H01L2224/4911 , H01L2224/49171 , H01L2224/73265 , H01L2224/83051 , H01L2224/92247 , H01L2924/01013 , H01L2924/01078 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PURPOSE:To facilitate the bonding of a wire to a die mounting part, by providing a semiconductor package with a region which hardly permits a bonding material to be wet in a die bonding operation but allows a wire bonding. CONSTITUTION:In a die mounting part 1, an Al layer 8 is provided outside bonding parts by evaporation or plating which prevents solder from wetting but permits a wire bonding. The layer 8 blocks the flowage of the molten solder, and it is made possible to bond a thin metal wire 9 to the layer 8 in the mounting part 1. Accordingly, the operation is facilitated.
摘要翻译：目的：为了使导线与模具安装部分的接合，通过在芯片接合操作中提供几乎不允许接合材料湿润的区域的半导体封装，但允许引线接合。构成：在模具安装部1中，通过蒸镀或电镀将Al层8设置在接合部的外侧，防止焊料润湿，但允许引线接合。层8阻止熔融焊料的流动，并且可以将薄金属线9粘合到安装部分1中的层8上。因此，操作便利。

8. 发明专利

JPS58180047A Manufacture of semiconductor package and semiconductor device 失效
标题翻译：半导体封装和半导体器件的制造
公开(公告)号：JPS58180047A
公开(公告)日：1983-10-21
申请号：JP6375382
申请日：1982-04-15
申请人： Matsushita Electric Ind Co Ltd
发明人： HIRAI MINORU , ITOU SUMIE
IPC分类号： H01L23/12 , H01L23/50 , H01L23/58
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE:To prevent destruction of the semiconductor element and deterioration of the electric characteristic of the semiconductor device by a method wherein the whole electrodes of the dual-in-line type hollow package are short-circuited in the progress of assembling work. CONSTITUTION:One electrode 8 out of the electrodes connected to the outside electrodes 4 side out of the inside electrode group 3, and one electrode 9 out of the electrodes connected to the outside electrodes 5 side out of the inside electrodes 3 are connected by a connecting wire 10. As the material of the connecting wire 10, a conductor being sufficiently fine and meltable at a low temperature is used, for example, and the material being meltable to be cut off by heating the package itself after completion of assembling is used. Accordingly the semiconductor element is made to be in the condition being exhibitable normal performance after melting off of the connecting wire 10. As the material of the connecting wire 10 mentioned above, to use a conductor sufficiently fine as compared with a bonding wire and easily cuttable by a minute current, and to use structure enabled to cut the conductor wire 10 by flowing a current from the outside after completion of assembling is also favorable.
摘要翻译：目的：为了防止半导体元件的破坏和半导体器件的电特性的恶化，其中双列直插型中空封装的整个电极在组装工作进行中短路的方法。构成：从外部电极组3的外部电极4侧的电极中的一个电极8，与外部电极5侧的连接到内部电极3的电极中的一个电极9通过连接作为连接线10的材料，例如使用足够细小且可在低温下熔化的导体，并且使用在组装完成之后通过加热封装本身来可熔断的材料被切断。因此，使半导体元件处于连接线10熔断后呈现正常性能的状态。作为上述连接线10的材料，使用与接合线相比足够细的导体并且易于切割并且通过在组装完成之后通过从外部流动电流来使能能够切断导线10的结构也是有利的。

9. 发明专利

JPH0512854B2 失效
公开(公告)号：JPH0512854B2
公开(公告)日：1993-02-19
申请号：JP5946884
申请日：1984-03-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIRAI MINORU , HATADA KENZO
IPC分类号： H01L21/60

10. 发明专利

JPH0158865B2 失效
公开(公告)号：JPH0158865B2
公开(公告)日：1989-12-13
申请号：JP21980883
申请日：1983-11-22
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HATADA KENZO , HIRAI MINORU
IPC分类号： H01L21/60

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