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1. 发明专利

JP2006080424A Wiring board and its manufacturing method 审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2006080424A
公开(公告)日：2006-03-23
申请号：JP2004265105
申请日：2004-09-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SUGAWA TOSHIO , HIGASHIYA HIDEKI , MISAKI TAKUMI
IPC分类号： H05K3/24 , H05K3/06 , H05K3/38
CPC分类号： H05K1/0242 , H05K1/0237 , H05K3/108 , H05K3/181 , H05K3/24 , H05K3/381 , H05K3/383 , H05K3/384 , H05K3/4069 , H05K2201/0338 , H05K2201/0355 , H05K2201/098 , H05K2203/0307 , H05K2203/0392 , Y10T29/49126 , Y10T29/49128 , Y10T29/49133
摘要： PROBLEM TO BE SOLVED: To cause an unevenness not to be formed in the passing direction of the electric signal of a wiring, and to increase a surface area in section without changing the distance of the wiring, whereby an insulating board is adhered to a first conductive layer with no clearance to enhance an adhering force. SOLUTION: The wiring board is formed with a first conductive layer 7 and a second conductive layer 9 on an insulating board 1. In the section of a boundary between the first conductive layer 7 and the second conductive layer 9, at least the surface of the first conductive layer 7 is smaller than a side coming into contact with the insulating board 1, and a third conductive layer 11 is formed so as to coat surfaces of the first and second conductive layers. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了在布线的电信号的通过方向上不形成不均匀性，并且在不改变布线的距离的情况下增加截面的表面积，从而绝缘板被粘附到没有间隙的第一导电层以增强附着力。解决方案：布线板在绝缘板1上形成有第一导电层7和第二导电层9.在第一导电层7和第二导电层9之间的边界部分中，至少第一导电层7的表面小于与绝缘板1接触的一面，并且形成第三导电层11以便涂覆第一和第二导电层的表面。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005150447A Wiring board and its manufacturing method 审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2005150447A
公开(公告)日：2005-06-09
申请号：JP2003386646
申请日：2003-11-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIGASHIYA HIDEKI , SUGAWA TOSHIO , SASAKI TOMOE
IPC分类号： H05K3/40 , H05K3/20 , H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board of an all-layer IVH structure at a high density in which, even when a wiring is made finer, a sufficiently wiring adhesion strength can be ensured; and to provide its manufacturing method. SOLUTION: The wiring board comprises electrically insulating substrates 1, 7 of one layer or more and a wiring pattern formed on at least one face of the electrically insulating substrates 1, 7. A side face of the wiring pattern is subjected to an adhesion process which differs from an adhesion process which is performed on front and rear surfaces of the wiring pattern, and the adhesion process which differs from that on the front and rear surfaces of the wiring pattern is performed on an end face of the wiring pattern, thereby further enhancing the adhesion strength of the wiring. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供高密度的全层IVH结构的多层布线板，其中即使布线更细，可以确保足够的布线粘合强度; 并提供其制造方法。解决方案：布线板包括一层或多层的电绝缘基板1,7和形成在电绝缘基板1,7的至少一个面上的布线图案。布线图案的侧面经受在布线图案的端面上进行与布线图案的前表面和背面的粘附处理不同的附着处理和与布线图案的表面和背面不同的粘合处理，从而进一步提高布线的粘合强度。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005093513A Wiring board, its manufacturing method, and electronic part mounting body using the same 有权
标题翻译：接线板及其制造方法及使用其的电子部件安装体
公开(公告)号：JP2005093513A
公开(公告)日：2005-04-07
申请号：JP2003321333
申请日：2003-09-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIGASHIYA HIDEKI , ANPO TAKEO
IPC分类号： H05K1/16 , H05K1/02 , H05K3/14 , H05K3/24 , H05K3/32 , H05K3/38 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To realize the formation of a fine interconnect line and a stable interlayer connection simultaneously so as to provide a wiring board which displays high interlayer connection reliability and has a uniform connection resistance.
SOLUTION: The wiring board is equipped with an electric insulating base 101, interconnect lines arranged on both the sides of the electric insulating base 101, through-holes 103 bored in the electric insulating base 101 penetrating through it, and conductors 104 filling up the through-holes 103. The interconnect lines formed on the sides of the insulating base 101 are electrically connected together with the conductors 104. At least, either of the interconnect lines formed on the sides of the base 101 is a thin film interconnect line 102 formed through a vacuum film deposition method.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：同时实现精细互连线和稳定的层间连接的形成，以提供显示出高层间连接可靠性并具有均匀连接电阻的布线板。布线板配有电绝缘基座101，布置在电绝缘基座101的两侧的布线，穿透电绝缘基座101的通孔103和填充的导体104 形成在绝缘基底101的侧面上的互连线与导体104电连接在一起。至少，形成在基底101的侧面的互连线中的至少一个是薄膜互连线 102通过真空膜沉积法形成。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2003014672A Method for judging surface of metal, printed circuit board and method for manufacturing multilayer circuit board 审中-公开
标题翻译：用于判断金属表面的方法，印刷电路板和制造多层电路板的方法
公开(公告)号：JP2003014672A
公开(公告)日：2003-01-15
申请号：JP2001199939
申请日：2001-06-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIGASHIYA HIDEKI , KOKUBU SHINOBU
IPC分类号： G01N23/227 , G01N1/28 , G01N23/225 , H05K1/11 , H05K3/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for quantitatively judging the uppermost surface state of a metal to become a wiring material and to suppress a product unevenness of a printed circuit board.
SOLUTION: The method for judging the surface of the metal comprises the steps of detecting a photoelectron to be irradiated from the surface of the metal by irradiating the surface of the metal 201 to be judged with an X-ray, and thereby analyzing the surface of the metal. The method further comprises a step of selectively removing the surface of the metal 201 to be judged. The method also comprises the steps of irradiating the exposed surface of the metal 201 exposed by the selective removal of the surface of the metal 201 with the X-ray, detecting the photoelectron irradiated from the exposed surface, and thereby analyzing the exposed surface (therein). The method also comprises the steps of comparing the surface analyzed result of the metal 201 with the analyzed result of the exposed surface, and thereby judging the surface state.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种定量判断金属成为配线材料的最上表面状态并抑制印刷电路板的产品不均匀性的方法。解决方案：用于判断金属表面的方法包括以下步骤：通过用X射线照射要判断的金属201的表面来检测从金属表面照射的光电子，从而分析金属。该方法还包括选择性地去除要判断的金属201的表面的步骤。该方法还包括以下步骤：通过用X射线选择性去除金属201的表面而暴露的金属201的暴露表面，检测从暴露表面照射的光电子，从而分析暴露的表面（其中）。该方法还包括以下步骤：将金属201的表面分析结果与暴露表面的分析结果进行比较，从而判断表面状态。

5. 发明专利

JP2002319763A MULTILAYER WIRING BOARD AND ITS PRODUCING METHOD 失效
公开(公告)号：JP2002319763A
公开(公告)日：2002-10-31
申请号：JP2001125397
申请日：2001-04-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIGASHIYA HIDEKI , NAKAMURA SADASHI , ANDO DAIZO
IPC分类号： H05K1/11 , H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board in which the wiring containability of an inner layer is enhanced at a part crowded with through holes, while making the most of a feature that electrical connection can be realized through a conductor obtained by filling a through hole made between arbitrary layers of a conventional structure. SOLUTION: Electric insulating basic material 101, each provided with conductor wiring 104 on at least one of the opposite faces, are laid in layer, through holes 102 and 105 are made between the opposite faces of the electric insulating basic material, and then electrical connection is made between the layers of the conductor wiring 104 through a conductor 103 filling the through hole. In such a multilayer wiring board, at least one through hole 102 penetrates a plurality of layers of the electric insulating basic material 101 and electrical connection of the conductor wiring 104, 104 provided on the opposite sides of the through hole 102 in the penetrating direction is made through the conductor 103 filling the through hole 102.

6. 发明专利

JP2002319751A WIRING BOARD AND ITS PRODUCING METHOD 失效
公开(公告)号：JP2002319751A
公开(公告)日：2002-10-31
申请号：JP2001125398
申请日：2001-04-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAKAMURA SADASHI , ANDO DAIZO , HIGASHIYA HIDEKI
IPC分类号： H05K1/11
摘要： PROBLEM TO BE SOLVED: To solve a problem that, when a wiring pattern is sufficiently larger than the area of a via hole, adhesive cannot be discharged sufficiently from between the wiring pattern and an insulating basic material at the time of burying the wiring pattern in adhesive layer and, since the burying quantity of the wiring pattern is insufficient, a compressing force does not act sufficiently onto a conductive material 4 in a through hole and, since the conductor component of the conductive material 4 is not made compact easily, initial connection resistance increases and connection reliability of via hole is damaged. SOLUTION: Even if a land 2 of different area exists in the same insulation layer 1, a large connection area is ensured between the land 2 and an interlayer connector, by increasing or decreasing the area of connection face of the interlayer connector or forming an interlayer connector having a connection face of linear shape. Consequently, initial connection resistance can be settled at a low level while ensuring connection reliability of via hole.

7. 发明专利

JP2002314223A METHOD FOR FORMING PATTERN OF CIRCUIT BOARD 失效
公开(公告)号：JP2002314223A
公开(公告)日：2002-10-25
申请号：JP2001117839
申请日：2001-04-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUOKA SUSUMU , OKIMOTO RIKIYA , HIGASHIYA HIDEKI
IPC分类号： H05K3/06
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a pattern of copper and a copper alloy capable of preventing a short circuit between wirings or a wiring thinning fault due to overetching from occurring in the formation of the fine pattern of forming the pattern of a circuit board. SOLUTION: The method for forming the pattern of the circuit board comprises the steps of forming the pattern by a plurality of etching liquids having different dissolving speeds of the copper and the copper alloy or an etching method.

8. 发明专利

JP2002161379A ETCHING APPARATUS AND METHOD FOR MANUFACTURING ETCHED SUBSTRATE THEREWITH 失效
公开(公告)号：JP2002161379A
公开(公告)日：2002-06-04
申请号：JP2000351306
申请日：2000-11-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIGASHIYA HIDEKI , MATSUOKA SUSUMU
IPC分类号： C23F1/08 , H05K3/06
摘要： PROBLEM TO BE SOLVED: To provide an etching apparatus which can accurately control an etching condition and can stably form a fine wiring, and to provide a method for manufacturing an etched substrate. SOLUTION: This etching apparatus comprises arranging substrate thickness measuring means 9 and 10 inside of and at a mouth of an etching area 8, and controlling a transferring speed of a substrate 7 based on a measured result with the measuring means, to control the etching condition thereby. The etching apparatus includes measuring a thickness of the substrate 7 before etching with the thickness measuring means 10, measuring the thickness of the substrate 7 on the way of etching with the thickness measuring means 9, and calculating an etched quantity by comparing the both measured result, to control the etching condition.

9. 发明专利

JP2000277889A TRANSFER MEDIUM, MANUFACTURE OF THE TRANSFER MEDIUM AND MANUFACTURE OF WIRING PATTERN USING THE TRANSFER MEDIUM 失效
公开(公告)号：JP2000277889A
公开(公告)日：2000-10-06
申请号：JP8247599
申请日：1999-03-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SUGAWA TOSHIO , ANDO DAIZO , NAKAMURA SADASHI , HIGASHIYA HIDEKI
IPC分类号： H05K3/20 , H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To manufacture a fine circuit board with satisfactory yield without generating disconnections, deformation or the like of a fine wiring pattern by a method, wherein a transfer medium in which a conductive layer is formed on the whole face of a substrate to be in a desired pattern and in which a conductive interconnection in a desired pattern is formed on the surface of the conductive layer is used and a transfer medium, in which at least a conductive interconnection and a substrate can be removed selectively by different etchants, is used. SOLUTION: A Zn-based conductive layer 103 is formed by an electroplating on the surface of an Al substrate 101. In addition, a desired pattern by a photosensitive resin 104 is formed on the surface of the conductive layer. A Cu conductive interconnection 105 is formed in a region, in which the surface of the conductive layer is exposed after the pattern is formed. The photosensitive resin is removed by an alkaline aqueous solution. Thereby, a transfer medium is manufactured. After the conductive interconnection of the transfer medium is buried in an insulating board, the conductive layer and the substrate are removed with hydrochloric acid, and a desired wiring pattern is obtained.

10. 发明专利

JPH1041771A MANUFACTURE OF VIBRATOR AND MANUFACTURE DEVICE THEREFOR 失效
公开(公告)号：JPH1041771A
公开(公告)日：1998-02-13
申请号：JP19426896
申请日：1996-07-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIGASHIYA HIDEKI
IPC分类号： H03H3/02
摘要： PROBLEM TO BE SOLVED: To improve the yield of a vibrator by measuring the thickness or oscillation frequency of the plural vibration parts of a diaphragm in a large plate shape, covering the specified vibration part of the diaphragm with first resist and etching the non-covered part of the first resist thereafter. SOLUTION: By directly measuring the thickness of the plural vibration parts 7 of the diaphragm 22 in the large plate shape or measuring the frequency of the plural vibration parts 7 and converting it to the thickness, the thickness distribution of the vibration parts 7 of the diaphragm 22 in the large plate shape is measured, the thickness of the respective vibration parts 7 is ranked and a part for thinning the thickness of the vibration parts 7 of the diaphragm 22 in the large plate shape by etching is specified. Thereafter, resist is applied to the entire diaphragm 22 in the large plate shape, the part for thinning the thickness of the diaphragm 7 obtained by ranking is exposed and developed and the resist is removed. Then, the vibration parts 7 is thinned by etching. Thus, the thickness dispersion of the vibration parts 7 of the diaphragm 22 in the large plate shape is made small and as a result, defects by the frequency deviation of a vibrator are suppressed.

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