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1. 发明专利

JP2009246370A Microcomputer, and data processor 有权
标题翻译： MICROCOMPUTER和数据处理器
公开(公告)号：JP2009246370A
公开(公告)日：2009-10-22
申请号：JP2009100471
申请日：2009-04-17
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： TANAKA TOSHIHIRO , UMEMOTO YUKIKO , HIRAKI MITSURU , SHINAGAWA YUTAKA , FUJITO MASAMICHI , SUZUKAWA KAZUFUMI , TANIGAWA HIROYUKI , YAMAKI TAKASHI , KAMIGAKI YOSHIAKI , MINAMI SHINICHI , KATAYAMA KOZO , MATSUZAKI NOZOMI
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L21/336 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device achieving high-speed stored information reading out of a nonvolatile memory cell. SOLUTION: A microcomputer includes an inner bus 68, a central arithmetic section 61 connected to the inner bus and a nonvolatile memory 63. The nonvolatile memory includes a plurality of nonvolatile memory cells having first and second gates, a first circuit 21 connected to the first gate of one of the plurality of nonvolatile memory cells, a second circuit connected to the second gate of one of the plurality of nonvolatile memory cells and a voltage generating circuit VS, 77 for generating a first voltage supplied to the first circuit and a second voltage supplied to the second circuit. The first circuit is lower than the second circuit in gate withstand voltage. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现从非易失性存储单元读出高速存储信息的半导体器件。解决方案：微型计算机包括内部总线68，连接到内部总线的中央运算部分61和非易失性存储器63.非易失性存储器包括具有第一和第二门的多个非易失性存储器单元，第一电路21连接连接到多个非易失性存储单元之一的第二栅极的第二电路和用于产生提供给第一电路的第一电压的电压产生电路VS，77，以及提供给第二电路的第二电压。第一电路低于栅极耐受电压中的第二电路。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2004164700A Nonvolatile semiconductor storage device and semiconductor integrated circuit device 有权
公开(公告)号：JP2004164700A
公开(公告)日：2004-06-10
申请号：JP2002326216
申请日：2002-11-11
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： YAMAKI TAKASHI , TANAKA TOSHIHIRO , SHINAGAWA YUTAKA
IPC分类号： G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To improve the rewriting durability of a memory cell and to remarkably improve the reliability for reading data. SOLUTION: A verify sense amplifier circuit 7 is arranged in a flash memory. The verify sense amplifier circuit 7 produces a discrimination current at verifying in accordance with the gate voltage Vgi produced by a voltage generating circuit. The level of this discrimination current is the current level at the same degree as those of respective memory currents of the memory cell S, capable of discriminating that the current at reading is flowing or not. Thus, by securing the memory current required for reading at verifying, the reliability of data reading is improved even for the memory cell S deteriorated by rewriting of data. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2007323684A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2007323684A
公开(公告)日：2007-12-13
申请号：JP2006149362
申请日：2006-05-30
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TANAKA TOSHIHIRO , TANIGAWA HIROYUKI , KATO AKIRA , YAMAKI TAKASHI , ISHIKAWA JIRO
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which a capacity element included in a charge pump circuit of an on-chipped nonvolatile memory can be minimized. SOLUTION: Inside of a semiconductor integration (1), when first power source voltage (Vcc) > second power source voltage (Vddm) > third power source voltage (Vddc) having comparatively different level can be utilized, in a memory power source circuit (33) generating high voltage for changing threshold voltage of a nonvolatile memory (4), relatively low power source voltage (Vddm) is used for the charge pump circuit (51) being required to suppress ripple of output voltage as a driver (51B) of a pump capacitor and area of a smoothing capacitor (53) is reduced, and relatively high level power source voltage (Vcc) is used for the charge pump circuit (52) being necessary current supply capability rather than suppression of ripple as a driver (52B) of the pump capacitor and area of a pump capacitor is reduced. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路，其中包含在片上非易失性存储器的电荷泵电路中的电容元件可以最小化。解决方案：在半导体集成（1）内部，当可以利用具有相对不同电平的第一电源电压（Vcc）>第二电源电压（Vddm）>第三电源电压（Vddc）时，在存储器功率产生用于改变非易失性存储器（4）的阈值电压的高电压的源极电路（33），为了抑制作为驱动器的输出电压的纹波，需要相对低的电源电压（Vddm）作为电荷泵电路（51） 51B）和平滑电容器（53）的面积减小，并且电荷泵电路（52）使用相对高电平的电源电压（Vcc）作为必需的电流供应能力，而不是抑制纹波为泵电容器的驱动器（52B）和泵电容器的面积减小。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007294105A Microcomputer 有权
标题翻译：微机
公开(公告)号：JP2007294105A
公开(公告)日：2007-11-08
申请号：JP2007179349
申请日：2007-07-09
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , YAMAKI TAKASHI , MAKUTA KIICHI , WADA MASASHI , KAWAJIRI YOSHIKI
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To shorten total writing time by a flash memory built in a microcomputer. SOLUTION: The microcomputer includes one semiconductor chip provided with a CPU and the flash memory. The flash memory includes a data register holding writing data provided from the CPU, a writing control circuit for performing continuous writing to a nonvolatile memory corresponding to a bit in which the writing data is at a second logic value by skipping the writing to the nonvolatile memory corresponding to a bit of a first logic value of the data held in the data register, and a decoder selecting a nonvolatile memory cell which is an object of writing operation. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过微型计算机内置的闪存缩短总写入时间。
解决方案：微计算机包括一个设置有CPU和闪存的半导体芯片。闪速存储器包括保存从CPU提供的写入数据的数据寄存器，写入控制电路，用于通过跳过对非易失性存储器的写入来对与写入数据处于第二逻辑值的位对应的非易失性存储器进行连续写入对应于保存在数据寄存器中的数据的第一逻辑值的一位，以及选择作为写入操作对象的非易失性存储单元的解码器。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006066009A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2006066009A
公开(公告)日：2006-03-09
申请号：JP2004250273
申请日：2004-08-30
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TANIGAWA HIROYUKI , TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , YAMAKI TAKASHI
IPC分类号： G11C16/02 , G06F12/00 , G06F12/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/344
摘要： PROBLEM TO BE SOLVED: To allow a non-volatile memory to perform high-speed read-out and assure a larger number of rewriting times. SOLUTION: The semiconductor integrated circuit has a non-volatile memory region (PGM) where information storage is performed by a difference in threshold voltages, and a second non-volatile memory region (DAT). The first non-volatile memory region is given a difference in any one condition among an erase verify judging memory gate voltage, erase verify judging memory current, write verify judging memory gate voltage, write verify judging memory current, erase voltage, erase voltage impression period, write voltage, and write voltage impression period, with respect to the second non-volatile memory region, so that the first non-volatile memory region is made faster in the read-out speed of the memory information than in the second non-volatile memory region, and the second non-volatile memory region is assured of a larger number of rewrite times than that in the first non-volatile memory region. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：允许非易失性存储器执行高速读出，并确保更多的重写次数。解决方案：半导体集成电路具有通过阈值电压差执行信息存储的非易失性存储区域（PGM）和第二非易失性存储区域（DAT）。在擦除验证判定存储器栅极电压，擦除验证判定存储器电流，写入验证判定存储器栅极电压，写入校验判定存储器电流，擦除电压，擦除电压印刷期间中的任何一个条件下给予第一非易失性存储器区域写入电压和写入电压压印周期相对于第二非易失性存储器区域，使得第一非易失性存储器区域在存储器信息的读出速度上比在第二非易失性存储器区域中的读取速度更快存储区域和第二非易失性存储器区域被确保比第一非易失性存储器区域中更多的重写时间。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2009252253A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009252253A
公开(公告)日：2009-10-29
申请号：JP2008094996
申请日：2008-04-01
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NITTA FUMIHIKO , IIDA YOSHIKAZU , YAMAKI TAKASHI , SONODA KENICHIRO
IPC分类号： G11C13/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a phase-change element can be changed into a crystal state in set operation even when the optimal crystal growth temperature range of the phase-change element varies. SOLUTION: In this phase-change memory, in the case of changing the phase-change element 5 from an amorphous state to the crystal state, after changing the temperature of the phase-change element 5 to nearly a fusing point by changing bit line voltage VBL to positive voltage Va and changing word line voltage VWL to the positive voltage Va, the temperature of the phase-change element 5 is lowered from nearly the fusing point to a temperature lower than a crystallization temperature by lowering the word line voltage VWL in a fixed inclination. Consequently, the temperature of the phase-change element 5 passes through the optimal crystal growth temperature range Tm in process of lowering, so that the phase-change element 5 can be changed into the crystal state. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其中即使当相变元件的最佳晶体生长温度范围变化时，相变元件也可以在设定操作中变为晶体状态。解决方案：在该相变存储器中，在将相变元件5从非晶状态改变为晶体状态的情况下，通过改变相变元件5的温度到接近熔点位线电压VBL变为正电压Va并将字线电压VWL改变为正电压Va，相变元件5的温度通过降低字线电压而从接近熔点降低到低于结晶温度的温度 VWL固定倾斜。因此，相变元件5的温度在降低的过程中通过最佳的晶体生长温度范围Tm，使得相变元件5可以变为晶体状态。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2005353159A Nonvolatile semiconductor memory and its writing method 有权
标题翻译：非线性半导体存储器及其写入方法
公开(公告)号：JP2005353159A
公开(公告)日：2005-12-22
申请号：JP2004172078
申请日：2004-06-10
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YASUI KAN , HISAMOTO MASARU , TANAKA TOSHIHIRO , YAMAKI TAKASHI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3418 , G11C16/0466 , G11C16/3427 , H01L27/115 , H01L29/4232 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent sequence disturbance which occurs dependent upon a path where biases in a standby state and a write state shift and in which a different memory cell on one and the same wordline is erroneously written or erased in a nonvolatile semiconductor memory device that uses a charge storage film. SOLUTION: In a procedure, a diffusion layer voltage Vs on a memory transistor side is changed and the gate voltage Vmg of the memory transistor is changed after the Vs exceeds the specified value Vsx of an intermediate stage regarding the rise and fall of a wordline bias. Alternatively, in a procedure, the gate voltage Vmg of the memory transistor is changed and the diffusion layer voltage Vs on the memory transistor side is changed after the Vmg exceeds the specified value Vmgx of an intermediate stage. The values Vsx and Vmgx are determined on the basis of the level of a gate insulating film electric field that does not cause FN electron injection which brings about a change in threshold voltage and the level of a potential barrier to a hole where a BTBT hot-hole injection does not occur. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止发生的序列干扰取决于在待机状态和写状态偏移处的偏差的路径，并且在一个和同一个字线上的不同存储器单元被错误地写入或擦除在非易失性存储器中的路径使用电荷存储膜的半导体存储器件。解决方案：在一个过程中，存储晶体管侧的扩散层电压Vs改变，并且在Vs超过关于上升和下降的中间阶段的规定值Vsx之后，存储晶体管的栅极电压Vmg改变字幕偏见或者，在程序中，在Vmg超过中间阶段的规定值Vmgx之后，存储晶体管的栅极电压Vmg改变，并且存储晶体管侧的扩散层电压Vs发生变化。基于不引起FN电子注入的栅极绝缘膜电场的电平来确定值Vsx和Vmgx，其导致阈值电压的变化和BTBT热敏电阻的孔的势垒的电平，空穴注入不会发生。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2009245589A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2009245589A
公开(公告)日：2009-10-22
申请号：JP2009176327
申请日：2009-07-29
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TANAKA TOSHIHIRO , YAMAKI TAKASHI , SHINAGAWA YUTAKA , OKADA DAISUKE , HISAMOTO MASARU , YASUI KAN , ISHIMARU TETSUYA
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To attain increase of a data writing speed and reduction of the power consumption by reducing variance in the fluctuation of threshold voltage of a nonvolatile memory cell when writing data. SOLUTION: When the data are written into a memory cell MM00, a voltage of 8V level is applied to a memory gate line MG0, a voltage of 5V level is applied to a source line SL0, a voltage of 1.5V level is applied to a selection gate line CG0 respectively. At this time, in a write-in circuit 9, the writing pulse is 0, an output of the writing latch 15 is Hi signal, an output of a NAND circuit 14 becomes Lo signal, a constant current of 1μA level flows into a constant current source transistor 12, and the bit line BL0 is discharged by a constant current of 1μA level to flow the current to the memory cell MM00. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：当写入数据时，通过减少非易失性存储器单元的阈值电压的波动的方差来实现数据写入速度的提高和功耗的降低。解决方案：当将数据写入存储单元MM00时，将8V电平的电压施加到存储器栅极线MG0，5V电平的电压施加到源极线SL0，1.5V电平的电压为分别施加到选择栅极线CG0。此时，在写入电路9中，写入脉冲为0，写入锁存器15的输出为Hi信号，NAND电路14的输出变为Lo信号，1μA电平的恒定电流流入常数电流源晶体管12，并且位线BL0以1μA电平的恒定电流放电，以将电流流向存储单元MM00。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2008286740A Semiconductor integrated circuit, and testing method therefor 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：JP2008286740A
公开(公告)日：2008-11-27
申请号：JP2007134121
申请日：2007-05-21
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KATO AKIRA , OKAZAKI TSUTOMU , YAMAKI TAKASHI , TANAKA TOSHIHIRO
IPC分类号： G01R31/28 , G06F11/22 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To highly precisely detect a leak current while detecting quickly the presence of short circuiting. SOLUTION: An LSI chip is provided with an internal circuit FLM of a testing object DUT, and a testing circuit BIST. The testing circuit BIST includes a variable current source 10, a voltage comparator 11, controllers 12, 16, and a supply circuit 14 for supplying an output current Iout to the internal circuit FLM. The output current Iout is set within a range from the maximum current Imax to the minimum current Imini by the controllers. A detection voltage Vsen of the supply circuit 14 and a reference voltage Vref thereof are supplied to the voltage comparator 11. The controllers set the output current Iout to the maximum current Imax to detect the presence of the short circuiting, and set the output current Iout to the minimum current Imini to detect the presence of the leak current. The both detections are carried out in the voltage comparator 11. The short circuiting in a wiring layer is quickly detected and the leak current is detected highly precisely. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：高速精确检测泄漏电流，同时快速检测短路的存在。解决方案：LSI芯片设置有测试对象DUT的内部电路FLM和测试电路BIST。测试电路BIST包括用于向内部电路FLM提供输出电流Iout的可变电流源10，电压比较器11，控制器12,16和电源电路14。输出电流Iout由控制器设定在从最大电流Imax到最小电流Imini的范围内。供给电路14的检测电压Vsen及其基准电压Vref被提供给电压比较器11.控制器将输出电流Iout设定为最大电流Imax，以检测短路的存在，并将输出电流Iout 到最小电流Imini来检测泄漏电流的存在。在电压比较器11中进行两个检测。快速检测布线层的短路，高精度地检测漏电流。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2008097758A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008097758A
公开(公告)日：2008-04-24
申请号：JP2006280489
申请日：2006-10-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： UMEMOTO YUKIKO , KATO AKIRA , TANAKA TOSHIHIRO , ISHIKAWA JIRO , YAMAKI TAKASHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To achieve a high reading speed by securing a sufficient reading current without reducing reliability. SOLUTION: The semiconductor memory device where nonvolatile memory cells (mm0 to mm15) including control gate and memory gate electrodes to which predetermined voltages are supplied in writing, erasing and reading operations are formed, is provided with a control circuit for increasing reading currents from the memory cells by increasing the potential of the memory gate electrode by coupling the control gate and memory gate electrodes when data are read from the nonvolatile memory cells. A high reading speed is achieved by securing a sufficient reading current by coupling the control gate and memory gate electrodes. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过确保足够的读取电流而不降低可靠性来实现高读取速度。解决方案：形成包括在写入，擦除和读取操作中提供预定电压的控制栅极和存储栅电极的非易失性存储单元（mm0至mm15）的半导体存储器件，其具有用于增加读数的控制电路通过在从非易失性存储器单元读取数据时通过耦合控制栅极和存储器栅极电极来增加存储栅电极的电位从存储单元的电流。通过连接控制栅极和存储栅电极来确保足够的读取电流来实现高读取速度。版权所有（C）2008，JPO＆INPIT

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