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1. 发明专利

JP2007294105A Microcomputer 有权
标题翻译：微机
公开(公告)号：JP2007294105A
公开(公告)日：2007-11-08
申请号：JP2007179349
申请日：2007-07-09
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , YAMAKI TAKASHI , MAKUTA KIICHI , WADA MASASHI , KAWAJIRI YOSHIKI
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To shorten total writing time by a flash memory built in a microcomputer. SOLUTION: The microcomputer includes one semiconductor chip provided with a CPU and the flash memory. The flash memory includes a data register holding writing data provided from the CPU, a writing control circuit for performing continuous writing to a nonvolatile memory corresponding to a bit in which the writing data is at a second logic value by skipping the writing to the nonvolatile memory corresponding to a bit of a first logic value of the data held in the data register, and a decoder selecting a nonvolatile memory cell which is an object of writing operation. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过微型计算机内置的闪存缩短总写入时间。
解决方案：微计算机包括一个设置有CPU和闪存的半导体芯片。闪速存储器包括保存从CPU提供的写入数据的数据寄存器，写入控制电路，用于通过跳过对非易失性存储器的写入来对与写入数据处于第二逻辑值的位对应的非易失性存储器进行连续写入对应于保存在数据寄存器中的数据的第一逻辑值的一位，以及选择作为写入操作对象的非易失性存储单元的解码器。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2009246370A Microcomputer, and data processor 有权
标题翻译： MICROCOMPUTER和数据处理器
公开(公告)号：JP2009246370A
公开(公告)日：2009-10-22
申请号：JP2009100471
申请日：2009-04-17
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： TANAKA TOSHIHIRO , UMEMOTO YUKIKO , HIRAKI MITSURU , SHINAGAWA YUTAKA , FUJITO MASAMICHI , SUZUKAWA KAZUFUMI , TANIGAWA HIROYUKI , YAMAKI TAKASHI , KAMIGAKI YOSHIAKI , MINAMI SHINICHI , KATAYAMA KOZO , MATSUZAKI NOZOMI
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L21/336 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device achieving high-speed stored information reading out of a nonvolatile memory cell. SOLUTION: A microcomputer includes an inner bus 68, a central arithmetic section 61 connected to the inner bus and a nonvolatile memory 63. The nonvolatile memory includes a plurality of nonvolatile memory cells having first and second gates, a first circuit 21 connected to the first gate of one of the plurality of nonvolatile memory cells, a second circuit connected to the second gate of one of the plurality of nonvolatile memory cells and a voltage generating circuit VS, 77 for generating a first voltage supplied to the first circuit and a second voltage supplied to the second circuit. The first circuit is lower than the second circuit in gate withstand voltage. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现从非易失性存储单元读出高速存储信息的半导体器件。解决方案：微型计算机包括内部总线68，连接到内部总线的中央运算部分61和非易失性存储器63.非易失性存储器包括具有第一和第二门的多个非易失性存储器单元，第一电路21连接连接到多个非易失性存储单元之一的第二栅极的第二电路和用于产生提供给第一电路的第一电压的电压产生电路VS，77，以及提供给第二电路的第二电压。第一电路低于栅极耐受电压中的第二电路。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009176419A Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：JP2009176419A
公开(公告)日：2009-08-06
申请号：JP2009116104
申请日：2009-05-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： FUJITO MASAMICHI , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , SANO AYAKO , KATO AKIRA , TANAKA TOSHIHIRO
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To achieve a high reading speed in an electrically rewritable on-chip nonvolatile memory. SOLUTION: The data processor is provided with a central processing unit and an accessible nonvolatile storage circuit. In the nonvolatile storage circuit, each memory cell is coupled with one first bit line corresponding to a plurality of first bit lines, and each of two first bit lines is coupled with one corresponding first amplifier circuit via a selection circuit. The first amplifier circuit is coupled with a plurality of corresponding second bit lines and the second bit lines are coupled with a plurality of corresponding second amplifier circuits, and the second amplifier circuits are coupled with a bus. In a reading operation, the selection circuits couples the two first bit lines with one corresponding first amplifier circuit. In a writing operation, each of the two memory cells coupled with the two first bit lines coupled with one first amplifier circuit stores different data. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在电可重写片上非易失性存储器中实现高读取速度。解决方案：数据处理器具有中央处理单元和可访问的非易失性存储电路。在非易失性存储电路中，每个存储单元与对应于多个第一位线的一个第一位线耦合，并且两个第一位线中的每一个经由选择电路与一个对应的第一放大器电路耦合。第一放大器电路与多个对应的第二位线耦合，并且第二位线与多个对应的第二放大器电路耦合，并且第二放大器电路与总线耦合。在读取操作中，选择电路将两个第一位线与一个对应的第一放大器电路耦合。在写入操作中，与与一个第一放大器电路耦合的两个第一位线耦合的两个存储器单元中的每一个存储不同的数据。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2004318941A Semiconductor integrated circuit 有权
公开(公告)号：JP2004318941A
公开(公告)日：2004-11-11
申请号：JP2003108604
申请日：2003-04-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： FUJITO MASAMICHI , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , SANO AYAKO , KATO AKIRA , TANAKA TOSHIHIRO
IPC分类号： G11C16/06 , G11C7/18 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/30
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/30 , G11C2207/005 , G11C2216/22
摘要： PROBLEM TO BE SOLVED: To speed up a reading speed of electrically rewritable on-chip nonvolatile memory. SOLUTION: The nonvolatile memory has a hierarchized bit line structure comprising a first bit line (BL) unique to each of two or more memory arrays (21), a second bit line (GBLr) common to the two or more memory arrays, a first selection circuit which selects the first bit line for each memory array and is able to connect it to the second bit line, and a sense amplifier (SA) arranged between the output of the first selection circuit (22) and the second bit line. The hierarchized bit line structure by the division of the memory arrays reduces the input load capacity of the sense amplifier. COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2004281014A Integrated semiconductor circuit 审中-公开
标题翻译：集成半导体电路
公开(公告)号：JP2004281014A
公开(公告)日：2004-10-07
申请号：JP2003074826
申请日：2003-03-19
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： FUJITO MASAMICHI , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , SANO AYAKO , TANAKA TOSHIHIRO
IPC分类号： G01R31/28 , G06F15/78 , G11C16/02 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/02 , G11C29/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide an integrated semiconductor circuit that can prevent defects from spreading by high voltage applied to a defective memory cell. SOLUTION: This integrated circuit drives a plurality of first memory blocks (MBLK0-MBLKk), a second memory block (RBLK), and the above second memory block instead of the first memory block which has defects, and has a non-volatile memory which includes logic circuits (MDD0-MDDk, RDD) to suppress the operation of the defective first memory. Each memory block has an array of non-volatile memory cells (MC) which are electrically erasable and writable. Each array is equally formed in a configuration of units of gate control wires (WL to WK , ML, ...) connected to the gate electrodes of the non-volatile memory cells. For the first high voltage isolation system, the above gate control wires are separated between the above memory blocks. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种集成半导体电路，其可以防止由于施加到有缺陷的存储单元的高电压而导致的缺陷扩散。解决方案：该集成电路驱动多个第一存储器块（MBLK0-MBLKk），第二存储器块（RBLK）和上述第二存储器块而不是具有缺陷的第一存储器块，包括用于抑制有缺陷的第一存储器的操作的逻辑电路（MDD0-MDDK，RDD）的易失性存储器。每个存储块具有可电可擦除和可写的非易失性存储单元阵列（MC）。每个阵列以连接到非易失性存储单元的栅电极的栅控制线（WL <0>至WK ，ML，...）的单元的结构相同地形成。对于第一高压隔离系统，上述门控制线在上述存储块之间分离。版权所有（C）2005，JPO＆NCIPI

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