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1. 发明专利

JP2004103657A Semiconductor storage device 有权
公开(公告)号：JP2004103657A
公开(公告)日：2004-04-02
申请号：JP2002260279
申请日：2002-09-05
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KAJITANI KAZUHIKO , NODA HIROMASA , MIYATAKE SHINICHI , TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , SAKATA TAKESHI
IPC分类号： H01L21/8242 , G11C5/06 , G11C7/18 , G11C11/22 , G11C11/401 , G11C11/4097 , G11C29/50 , H01L27/02 , H01L27/108
CPC分类号： G11C29/50 , G11C7/18 , G11C11/4097 , G11C2207/005 , G11C2211/4013 , H01L27/0207 , H01L27/10882 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To reduce the contact resistance of each bit line selecting switch and to make the on-resistances of all bit line selecting switches uniform without making an area required for arranging the switches larger.
SOLUTION: The bit line selecting switches 14 are connected to one-side ends of odd-numbered bit lines 12 and to the other-side ends of even-numbered bit lines 12. The odd-numbered and even-numbered bit lines 12 are connected to terminals of sense amplifiers 16 one pair by one pair. Memory cells 13 are arranged at prescribed intersecting points of word lines 11 and bit lines 12 corresponding to a half of all intersecting points of the lines 11 and 12, so that the memory cells 13 connected to one word line 11 are connected electrically to each terminal of a unit circuit 16 one by one when the word line 11 is selected.
COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2003273245A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2003273245A
公开(公告)日：2003-09-26
申请号：JP2002071254
申请日：2002-03-15
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MIYATAKE SHINICHI , KAJITANI KAZUHIKO , MIYAZAWA KAZUYUKI , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , SAKATA TAKESHI
IPC分类号： G11C11/401 , G11C7/18 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/119
CPC分类号： H01L27/108 , G11C7/18 , G11C11/403 , G11C11/406 , G11C11/40615 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10897 , Y10S257/905 , Y10S257/906
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which high integration and a very high speed are obtained and further, power consumption when holding information is remarkably reduced by suppressing an increase in the area of memory cell, obtaining a very high speed read time and further, securing a long refresh time in the case of self-refresh.
SOLUTION: In a twin cell structure using a single intersection 6F
2 -cell system in a DRAM using a single intersection 2-cell/bit system, memory cells MC are located at positions corresponding to all the intersections of bit line couples BL and /BL and word lines WL and when the half of a pitch of the word line WL is defined as F, a pitch of the bit line of the bit line couples BL and /BL is made larger than 2F and smaller than 4F. Further, an active area AA on a silicon wafer to form sources, channels and drains of transistors of the memory cells MC is formed obliquely to the direction of the bit line couples BL and /BL.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供一种获得高集成度和非常高的速度的半导体存储器件，并且通过抑制存储器单元的面积的增加，显着地减少了保持信息时的功耗，从而获得非常大的高速读取时间，进一步，在自刷新的情况下保证长时间的刷新时间。解决方案：在使用单交叉2单元/位系统的DRAM中使用单交叉6F 2 - 单元系统的双单元结构中，存储单元MC位于对应于所有位线耦合BL和/ BL与字线WL的交叉点，并且当字线WL的音调的一半被定义为F时，位线耦合BL和/ BL的位线的间距大于 2F，小于4F。此外，在硅晶片上形成存储单元MC的晶体管的源极，通道和漏极的有源区AA相对于位线耦合BL和/ BL的方向倾斜地形成。版权所有（C）2003，JPO

3. 发明专利

JP2011014210A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011014210A
公开(公告)日：2011-01-20
申请号：JP2009159413
申请日：2009-07-06
申请人： Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： SAKATA TAKESHI , YAMAOKA MASANAO
IPC分类号： G11C11/41
摘要： PROBLEM TO BE SOLVED: To provide an SRAM cell with small dimensions, capable of performing writing by using differential motion without having an effect of a path of write on a state held upon read.SOLUTION: The SRAM cell has NMOS drive transistors MDB and MDT and PMOS load transistors MLB and MLT as with a conventional 6 transistor SRAM cell, configures two CMOS inverters connected to a power line VDD and a ground line VSS, and holds data of one bit by positive feedback of cross-couple connection of the inverter pair. A transfer transistor MTB is connected to a bit line BLB via a write transistor MWB2 that is shared by two bits. A read transistor MRT and a write transistor MWT are connected to a bit line BLT side via a transfer transistor MTT. By sharing transistors between adjacent cells using the path of write, the number of transistors is reduced.
摘要翻译：要解决的问题：提供具有小尺寸的SRAM单元，能够通过使用差分运动执行写入，而不会在读取时保持写入路径的影响。解决方案：SRAM单元具有NMOS驱动晶体管MDB和MDT 和PMOS负载晶体管MLB和MLT，与传统的6晶体管SRAM单元一样，配置连接到电源线VDD和接地线VSS的两个CMOS反相器，并通过反相器对的交叉耦合连接的正反馈保持一位的数据。传输晶体管MTB通过由两位共享的写晶体管MWB2连接到位线BLB。读晶体管MRT和写晶体管MWT经由转移晶体管MTT连接到位线BLT侧。通过使用写入路径在相邻单元之间共享晶体管，减少了晶体管的数量。

4. 发明专利

JP2010097660A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010097660A
公开(公告)日：2010-04-30
申请号：JP2008268138
申请日：2008-10-17
申请人： Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： SAKATA TAKESHI , WADA SHOJI
IPC分类号： G11C11/407 , G11C11/4076 , G11C11/4093
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device incorporating a high-speed input interface for speeding up and improving the operating margin. SOLUTION: The semiconductor device has: a first and second pulse input circuits to input complementary first and second pulses after comparing them respectively with the reference voltage; and a plurality of data input circuits for taking in the input signals corresponding to the data consisting of a plurality of bits with their change start points made the same as the first and second pulses after comparing them with the reference voltage. It forms a third pulse having the change timing set up between the change timing of the output signal of the first pulse input circuit and the change timing of the output signal of the second pulse input circuit by using a phase interpolation circuit. It delays the third pulse for the predetermined time by using a delay circuit. Further, it takes in the output signal of the data input circuit by using a latch circuit corresponding to the change timing of the delay signal of the third pulse formed in the delay circuit. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种结合高速输入接口的半导体器件，用于加速和改善操作裕度。解决方案：半导体器件具有：第一和第二脉冲输入电路，用于在将它们分别与参考电压进行比较之后输入互补的第一和第二脉冲; 以及多个数据输入电路，用于将与由多个位组成的数据相对应的输入信号与第一和第二脉冲进行比较，并将其与参考电压进行比较之后，使它们的变化起始点相同。它通过使用相位插值电路形成具有在第一脉冲输入电路的输出信号的改变定时和第二脉冲输入电路的输出信号的改变定时之间设置的改变时序的第三脉冲。它通过使用延迟电路来延迟预定时间的第三脉冲。此外，它通过使用与延迟电路中形成的第三脉冲的延迟信号的改变定时相对应的锁存电路来接收数据输入电路的输出信号。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2004171742A Semiconductor device 审中-公开
公开(公告)号：JP2004171742A
公开(公告)日：2004-06-17
申请号：JP2003373026
申请日：2003-10-31
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , SAKATA TAKESHI , MIYATAKE SHINICHI , NODA HIROMASA , KAJITANI KAZUHIKO
IPC分类号： H01L21/8242 , G11C7/00 , G11C11/4076 , G11C11/409 , G11C11/4096 , H01L27/02 , H01L27/108 , H01L31/109
CPC分类号： G11C11/4096 , G11C11/4076 , G11C2207/002 , H01L27/0207 , H01L27/10882 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To realize both high-speed writing and stable rewriting in the DRAM of a high-speed cycle. SOLUTION: A word line and a Y selection line YS1 are simultaneously activated, write data is written from an IO line IOt/b in a selection data line DL1t/b, and the data of a memory cell is read at an adjacent nonselection amplifier. By dividing the source node of the cross couple CC of a sense amplifier connected to each data line pair for each Y selection line, the driving of the source node by a write selection cross coupling is prevented. The write data is written during reading, a high-speed writing operation is realized, and the driving of the source node by the write sense amplifier is prevented. Thus, at the adjacent sense amplifier, a stable reading operation is realized without being influenced by the write sense amplifier. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2014174670A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2014174670A
公开(公告)日：2014-09-22
申请号：JP2013045507
申请日：2013-03-07
申请人： Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： KAWAHIRA ICHITA , ABE SUSUMU , SAKATA TAKESHI
IPC分类号： G06F12/16
CPC分类号： Y02D10/13
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device including a memory circuit capable of reducing an increase in power consumption.SOLUTION: A semiconductor integrated circuit device includes an internal circuit and a memory module. The memory module has a plurality of memory circuits and is multiplexed so as to have identical data held at an identical address. If data is read from each of the memory circuits and it is determined on the basis of the data read from the memory circuits that there is a possibility of a failure in the memory circuits, then, a failure possibility signal is formed by a detection circuit. If the failure possibility signal is formed, a diagnostic operation is performed for the plurality of memory circuits. If the failure possibility signal is also formed in the diagnostic operation, an address signal specifying a different address is formed by a bad area management circuit.
摘要翻译：要解决的问题：提供一种包括能够减少功耗增加的存储电路的半导体集成电路器件。解决方案：一种半导体集成电路器件，包括内部电路和存储器模块。存储器模块具有多个存储器电路，并且被多路复用以具有保持在相同地址的相同数据。如果从每个存储器电路读取数据，并且基于从存储器电路读取的数据确定存在存储器电路存在故障的可能性，则由检测电路形成故障可能性信号。如果形成故障可能性信号，则对多个存储电路执行诊断操作。如果在诊断操作中也形成故障可能性信号，则由坏区管理电路形成指定不同地址的地址信号。

7. 发明专利

JP2011198441A Semiconductor device having nonvolatile memory containing fixed data 审中-公开
标题翻译：具有固定数据的非易失性存储器的半导体器件
公开(公告)号：JP2011198441A
公开(公告)日：2011-10-06
申请号：JP2010067198
申请日：2010-03-24
申请人： Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： YOSHIKAWA OUMI , SATO YOSHIO , SAKATA TAKESHI
IPC分类号： G11C11/22
摘要： PROBLEM TO BE SOLVED: To enable a nonvolatile RAM, such as an FeRAM, to quickly hold and present fixed data like a ROM, while securing the feature of a nonvolatile RAM capable of high-speed reading and writing.SOLUTION: The memory array of the FeRAM is divided into two groups. They are connected to two plate lines, a "0" writing plate line PL0, and a "1" writing plate line PL1 through the plate electrode switch SW, and the fixed data is written at once from the plate line.
摘要翻译：要解决的问题：使得诸如FeRAM之类的非易失性RAM能够在保证能够进行高速读取和写入的非易失性RAM的特征的同时，快速保持和呈现诸如ROM的固定数据。解决方案：存储器阵列 FeRAM分为两组。它们通过平板电极开关SW连接到两条板线，“0”字线PL0和“1”写板线PL1，并且从板线一次写入固定数据。

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