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    • 2. 发明专利
    • MULTIPLEX TRANSMITTING SYSTEM FOR DIGITAL SIGNAL
    • JPH06350547A
    • 1994-12-22
    • JP13311093
    • 1993-06-03
    • HITACHI LTD
    • TAKASAKI YOSHITAKA
    • H04J3/00H04J3/04
    • PURPOSE:To reduce the power consumption of circuit elements and to miniaturize a signal processor by interleaving plural digital information signals and multiplex frame control signals during a period of frame time and performing multiplex transmission. CONSTITUTION:A multiplex frame control signal generation circuit 2 generates a multiplex frame control signal mf by multiplexing frame control signals ap, bp and cp within a certain period of frame time. The bit rate of the control signal mf within one frame is equal to the bit rate of respective information signals. A multiplexer circuit 3 interleaves the signal mf and information trains (a), (b) and (c) at every bit. At such a time, a multiplex signal (m) is provided by extracting pulses in order of signals mf, (a), (b) and (c) and arranging 4 bits within a time slot T of one bit. The signal (m) is inputted through a transmission line 6 to a separation circuit 4 on a reception side and separated into the signal mf, (a), (b) and (c) and the signal mf is separated into frame control signals a'p, b'p and c'p by a frame separation circuit 5.
    • 7. 发明专利
    • COMMUNICATION METHOD
    • JPS6451743A
    • 1989-02-28
    • JP20811487
    • 1987-08-24
    • HITACHI LTD
    • TAKASE MASAHIKOTAKASAKI YOSHITAKA
    • H04L12/52H04Q11/04
    • PURPOSE:To attain efficient utilization by setting a path only when a call data transfer request exists and opening the path only when a call awaits the data transmission so as to apply intermittent transfer of lots of capacity data for plural calls by means of various network terminators in common. CONSTITUTION:When a call request comes from a terminal equipment 11, a subscriber line terminator 12 sends a call request to a line concentrator 13. The line concentrator 13 sends a synchronizing pattern to take frame synchronism of the subscriber link to the subscriber line terminator. The subscriber line terminator 12 informs the destination number and the communication mode identification signal to the network through the subscriber line signal channel. The line concentrator 13, exchanges 14, 14' and a receiver side line concentrator 13' use a destination number to select a path and to register the channel to adaptors 15, 15', 16, 16'. When the existing registration channel exists, it is arranged in a queue. When the queue is longer than a prescribed value, other channel is assigned newly.
    • 10. 发明专利
    • TIMING TRANSMISSION SYSTEM
    • JPS61182343A
    • 1986-08-15
    • JP2163085
    • 1985-02-08
    • HITACHI LTD
    • TAKASAKI YOSHITAKA
    • H04L7/00
    • PURPOSE:To improve the profitability and flexibility of the titled system by inserting a delay element into the timing system to attain the expansion of transmission range and release of limitation to a specific pattern in a digital transmission reception device producing a prescribed delay time between the reception and transmission for signal processing. CONSTITUTION:A reception signal from an input terminal 1 is amplified to a prescribed level by a receiver 2. Then a clock is extracted by a timing extraction circuit 3 and a signal decoded by a decoding circuit 5 is fed to a CPU7 via a logical circuit 6. On the other hand, a signal from a computer via the logical circuit is coded by a coding circuit 8 and sent from an output terminal 10 via a transmitter 9. Since the clock pulse used for logical processing in this system is delayed by a delay element 4 by a share of delay in the logical processing, no increasing in alignment jitter is incurred.