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1. 发明专利

JP2006262647A Apparatus controller 审中-公开
标题翻译：装置控制器
公开(公告)号：JP2006262647A
公开(公告)日：2006-09-28
申请号：JP2005077619
申请日：2005-03-17
申请人： Hitachi Ltd , Hitachi Vehicle Energy Ltd , Shin Kobe Electric Mach Co Ltd , 新神戸電機株式会社 , 日立ビークルエナジー株式会社 , 株式会社日立製作所
发明人： EMORI AKIHIKO , YAMAUCHI SHIYUUKO , ANDO KAZUMASA , KAWADA TAKAHIRO , IZUMI SHIHO
IPC分类号： H02J7/00 , B60H1/22 , B60L11/14 , B60R16/02 , B60R16/033 , B60R16/04 , F02D29/02 , F02D45/00
摘要： PROBLEM TO BE SOLVED: To provide an apparatus controller capable of performing control with good responsibility, by shortening the start time of a calculation processing means and of reducing the number of components, especially of electronic apparatus controller that is used as a battery controller for a battery power source, a power source controller, a temperature adjustment controller, and the like. SOLUTION: This apparatus controller is provided with a detection means for detecting physical quantities (voltage, current, temperature, for example) of a control apparatus, and a calculation processing means (a microcomputer 118) that calculates the state of the apparatus, based on the detected values of the physical quantity by the detection means. Furthermore, the controller comprises interlocked starting circuits (112, 113, 135) that monitor the changes in the detected values of the physical quantity by the detection means, and that start the calculation processing means due to the changes in the detected values. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够以良好的责任进行控制的装置控制器，通过缩短计算处理装置的开始时间和减少部件的数量，特别是用作电池的电子装置控制器用于电池电源的控制器，电源控制器，温度调节控制器等。解决方案：该装置控制器设置有用于检测控制装置的物理量（例如电压，电流，温度）的检测装置，以及计算装置的状态的计算处理装置（微型计算机118）基于检测单元检测到的物理量的值。此外，控制器包括互锁起动电路（112,113,135），其通过检测装置监视物理量的检测值的变化，并且由于检测值的变化而启动计算处理装置。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JPH1050072A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH1050072A
公开(公告)日：1998-02-20
申请号：JP22181996
申请日：1996-08-05
申请人： HITACHI LTD
发明人： FUJIMURA YASUHIRO , ANDO KAZUMASA
IPC分类号： G11C11/419
摘要： PROBLEM TO BE SOLVED: To stabilize the operation of a static type RAM by constituting a device based on a latch circuit in which a non-inversion and inversion input/ output nodes are directly and respectively coupled to non-inversion and inversion output nodes of a differential amplifier circuit. SOLUTION: In a unit sense amplifier latches USL0-USLk including a pair of cross-linked CMOS inverters, at the time of operation state, P and N channel MOSFET are complimentarily made an ON state, and their operation currents are made almost zero. Unit sense amplifiers USA0-USAk are directly connected to corresponding unit sense amplifier latches USL0-USLk without making through a bus MOSFET, but as a sense amplifier control signal SC2 is made a high level and MOSFET P1 and P2, P3 and P4, N3 and N4 are made an OFF state, relation between these unit sense amplifiers and the unit sense amplifier latches is made a complete cut off state.

3. 发明专利

JPH08236712A SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING IT 失效
公开(公告)号：JPH08236712A
公开(公告)日：1996-09-13
申请号：JP3857995
申请日：1995-02-27
申请人： HITACHI LTD
发明人： ANDO KAZUMASA , FUJIMURA YASUHIRO , AIHARA YOICHIRO
IPC分类号： H01L21/82 , H01L27/10
摘要： PURPOSE: To reduce power consumption at an unnecessary bit line without affecting the characteristics of a bit line clamp circuit by dividing a regulated current source of a bit line clamp circuit provided for each bit line into two parts to connect one regulated current source with non-used bit lines while separating the other regulated current source. CONSTITUTION: In an emitter follower part of a bit line clamp circuit 14 between two sets of regulated current sources 111, 112 and 121, 122 there are separated the latter sources. The remaining sources 111, 112 are designed to permit such a small current as 0.2mA to flow therethrough while the separated sources 121, 122 being designed to permit such a current as 0.6mA to flow therethrough. Accordingly, the bit line clamp circuit 14 corresponding to non-used bit lines has a consumed current reduced to about 1/4 compared with the bit line clamp circuit corresponding to the used bit lines. Further, since the regulated current sources 111, 112 are left behind in the bit line clamp circuit 14, potential of the non-used bit lines 15 is restricted not to float.

4. 发明专利

JPH0863244A CURRENT SOURCE CIRCUIT 失效
公开(公告)号：JPH0863244A
公开(公告)日：1996-03-08
申请号：JP20073394
申请日：1994-08-25
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , IDEI YOJI , MASUDA TORU , YAMAZAKI SU , OHATA KENICHI , KUSUNOKI TAKESHI , YAMAGUCHI KUNIHIKO , HIGETA KEIICHI , USAMI MASAMI , ANDO KAZUMASA
IPC分类号： G05F3/22 , H03F3/343
摘要： PURPOSE: To lower the source voltage of the current source circuit which is made small in the temperature dependency and source voltage dependency of a current value. CONSTITUTION: A start-up circuit SU which turns ON when the voltage difference between a source voltage VEE and a ground voltage reaches a specific voltage to supply a current and reaches high impedance when transistors(TR) Q2 and Q3 turn ON as a result and then TRs Q1 and QCS turn ON is connected to the bases of the Q2 and Q3. A current source I1 uses a current which flows when the Q2 turns ON. One end of a resistance RE is connected directly to the VEE and the other end is connected to the ground voltage through a high- impedance circuit (QCS, Q3, and I1) and also connected to the VEE thorugh a low-impedance circuit (QCS, Q3, Q2, R2, and Q1). The ratio of emitter current density of the Q1, Q2, Q3, and QCS is set to 1:1:1/20:1.

5. 发明专利

JPH09120683A DECODING CIRCUIT 失效
公开(公告)号：JPH09120683A
公开(公告)日：1997-05-06
申请号：JP30209995
申请日：1995-10-26
申请人： HITACHI LTD
发明人： ANDO KAZUMASA , USAMI MASAMI , YAMAGUCHI KUNIHIKO , IWABUCHI MASATO
IPC分类号： G11C11/413 , H03M7/00
摘要： PROBLEM TO BE SOLVED: To restrict an increase of a count of circuit elements and signal main lines and achieve high speeds, by providing a unit driving circuit wherein an output signal is turned to an effective level when a predetermined selection current is fed via an internal node, and a current sink circuit for selectively stopping the selection current. SOLUTION: A word line-driving circuit WD0-WD7 of an X address decoder XD consists of unit word line-driving circuits VD and a current sink circuit including a transistor T2 of transistors T3-T6. When a predetermined selection current flows via corresponding internal nodes n1-n4 set to word lines W000-W5111 of a memory array MARY, output signals, namely, word lines W000-W5111 are selectively turned to an effective level in the unit word line- driving circuit VD. Every two transistors are provided corresponding to each internal node n1-n4. The transistor T2 or T3-T6 selectively stops the selection current to be fed to the unit word line-driving circuit VD via the corresponding internal node n1-n4. Although three pre-decoders PDA-PDC dividing an internal address signal X0-X8 to every four, three and two bits are installed, the circuit Wd0-WD7 is logically constituted only in one stage as a decoding circuit.

6. 发明专利

JP2001057083A SEMI CONDUCTOR MEMORY 失效
公开(公告)号：JP2001057083A
公开(公告)日：2001-02-27
申请号：JP22770399
申请日：1999-08-11
申请人： HITACHI LTD
发明人： ANDO KAZUMASA
IPC分类号： G11C11/413 , G06F11/22 , G06F12/00 , G06F12/16 , G11C29/00 , G11C29/14
摘要： PROBLEM TO BE SOLVED: To shorten a cycle time of a static RAM incorporated in a logic integrated circuit as a macro-cell. SOLUTION: An enable-pulse ENP for making a word line a pulsative operation state during only the prescribed period is generated as a substantial AND signal of an internal clock signal ICLK and an inversion delay signal ICDB by its variable delay circuit VDL, while the device comprises a data comparing circuit making selectively a data coincidence signal DM a valid level when a test result is normal and a counter CTR receiving a valid level of the data coincidence signal DM and counting down it selectively, the device is provided with a pulse width control circuit PWC generating delay control signals DC 0-DCk of (k+1) bits as its output signal, the device has such a constitution that a delay time for an internal clock signal ICLK of the VDL is selectively switched conforming to DC0-DCk, further, a static RAM is provided with a function optimizing autonomously pulse width of the enable-pulse ENP in accordance with operation characteristics of relating circuits.

7. 发明专利

JPH10261289A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH10261289A
公开(公告)日：1998-09-29
申请号：JP8329397
申请日：1997-03-17
申请人： HITACHI LTD
发明人： ANDO KAZUMASA , KAWAGUCHI ETSUKO , HIGETA KEIICHI , FUJIMURA YASUHIRO
IPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To increase an operation speed of a synchronous SRAM and the like provided with a sense amplifier drive timing control section, to reduce its testing man-hours, and to reduce a manufacturing cost. SOLUTION: A test mode which is selectively specified by making a phase comparison disenable signal TPD supplied from an input terminal TPD an effective level is provided in a synchronous SRAM and the like. Also, in a sense amplifier drive timing control section SADC, a counter control signal CC for synchronizing-operating an up-down counter U/DC is formed based on a clock signal CK, that is, an internal clock signal CK1 at the time of an operation mode, and it is formed based on a test clock signal TCK supplied from an input terminal TCK at the time of a test mode. Further, an up signal UP or a down signal DN for counting up or counting down the up/down counter U/DC is formed conforming to an up signal up or a down signal dn outputted from a phase comparison circuit PC at the time of a normal operation mode, and it is formed conforming to a phase control signal TPC supplied from an input terminal TPC at the time of a test mode.

8. 发明专利

JPH0963279A SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING DEVICE 失效
公开(公告)号：JPH0963279A
公开(公告)日：1997-03-07
申请号：JP24364795
申请日：1995-08-29
申请人： HITACHI LTD
发明人： ANDO KAZUMASA , NISHIYAMA MASAHIKO
IPC分类号： G11C11/414 , G11C11/413 , H01L21/822 , H01L21/8229 , H01L27/04 , H01L27/102
摘要： PROBLEM TO BE SOLVED: To provide a technique for compensating for the saturation of a current-source transistor in a manner of circuitly. SOLUTION: The base electrodes of transistors 29, 39 are jointly connected to the output terminal 19 of a power source circuit 43 provided with a current- depending characteristic which lowers the output voltage V19 in accordance with an increase of the base current of the transistor 39. When the collector-base voltage Vcb of the transistor 39 decreases, feed-back control is made to increase the voltage so that saturation of the transistor 39 is compensated for by circuit action and the operational margin of ECL45 and also that of SRAM 73 including the ECL45 are improved.

9. 发明专利

JPH0832030A RESISTANCE ELEMENTS AND SEMICONDUCTOR DEVICE IN WHICH SAID ELEMENTS ARE INTEGRATED 失效
公开(公告)号：JPH0832030A
公开(公告)日：1996-02-02
申请号：JP16760794
申请日：1994-07-20
申请人： HITACHI LTD
发明人： ANDO KAZUMASA
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To provide a semiconductor device which restrains the influence upon the characteristics change of a semiconductor device to a minimum and improves the level of integration by facilitating reduction of the layout area of resistance elements with irregularity of resistance value kept restrained 4 to be small. CONSTITUTION:A resistance element 7 is constituted by burying a resistor 4 composed of polycrystalline semiconductor having a desired resistance value, in a vertical trench 2 of a substrate 1 composed of a semiconductor substrate, interposing an insulating film 3. The resistor 4 has a resistance width W in the vertical direction V of the substrate 1, and a resistance length L in the horizontal direction H of the substrate 1, and is doped with impurities. By setting the resistance width W large in the vertical direction V, a desired resistance value can be obtained while the resistance length L in the horizontal direction H is small. Thereby the layout area of the resistance element 7 is easily reduced. Since a desired resistance value is obtained by adjusting the dosage of impurities, irregurality of the resistance value can be restrained in a small range.

10. 发明专利

JPH11203877A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS DESIGN METHOD 失效
公开(公告)号：JPH11203877A
公开(公告)日：1999-07-30
申请号：JP749598
申请日：1998-01-19
申请人： HITACHI LTD
发明人： FUJIMURA YASUHIRO , ANDO KAZUMASA
IPC分类号： G11C11/419 , G11C11/401 , G11C11/407 , G11C11/41
摘要： PROBLEM TO BE SOLVED: To optimize activating timing of a sense amplifier for word line selecting timing without performing special tuning processing. SOLUTION: The device has a dummy memory cell 110 in which selecting timing is synchronized with word line selecting timing, level variation timing of a data line synchronizing with data read-out operation from a memory cell is simulated on a dummy data line DBL. A phase comparing circuit 130 indicates up-count or down-count to a counter 95 in accordance with phase difference between variation given to a dummy data line through selecting operation of the dummy memory cell and variation of a sense amplifier activating signal VDL, and a variable delay circuit 94 receiving the count value controls so as to cancel the phase difference and shift a time of activating timing by the sense amplifier activating signal.

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