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1. 发明专利

JP2003078415A Ad converter 有权
标题翻译： AD转换器
公开(公告)号：JP2003078415A
公开(公告)日：2003-03-14
申请号：JP2001261111
申请日：2001-08-30
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OTSUKA MASANORI , YAMAKIDO KAZUO , YAMAMOTO ETSUJI , SANO SHINYA
IPC分类号： H03M1/36
CPC分类号： H03M1/363
摘要： PROBLEM TO BE SOLVED: To provide an AD converter which does not need a buffer for an input signal or relieves a requirement specification such as an input signal range and an output impedance to a buffer. SOLUTION: A plurality of voltage comparators compare voltage of each connection point of a resistance ladder configured by serially connecting a plurality of resistive elements with a reference voltage, a high potential side of the resistance ladder is provided with a sweep-out type constant current circuit and a low potential side is provided with an attraction type constant current circuit respectively, and an input terminal is provided at an optional place other than both ends of the resistance ladder to supply an analog input voltage.
摘要翻译：要解决的问题：提供不需要用于输入信号的缓冲器的AD转换器，或者缓解对缓冲器的输入信号范围和输出阻抗的要求规范。解决方案：多个电压比较器比较通过串联连接多个电阻元件与参考电压构成的电阻梯的每个连接点的电压，电阻梯的高电位侧设置有扫除型恒流电路并且低电位侧分别设置有吸引型恒流电路，并且输入端子设置在电阻梯的两端以外的可选位置以提供模拟输入电压。

2. 发明专利

JPH10164089A ATM COMMUNICATION ADAPTER 失效
公开(公告)号：JPH10164089A
公开(公告)日：1998-06-19
申请号：JP32392696
申请日：1996-12-04
申请人： HITACHI LTD
发明人： JIKUYA TAKAYUKI , HATA EIZO , NAKAMURA HIROYUKI , TAKADA OSAMU , MIZUTANI MIKA , YOKOYAMA TATSUYA , YAMAKIDO KAZUO , NAGAYAMA YOSHIHARU
IPC分类号： G06F13/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide an ATM communication adapter capable of directly connecting an information processing terminal such as a notebook type personal computer or the like to an ATM network. SOLUTION: This adapter is an ATM-LAN card 2 connectable to the card bus 6 of 32 bits and loaded with a buffer memory 40 operated in a 16-bit width, an ATM controller 8, a processor 100 for communication control, a ROM 101, a RAM 102, a PMD semiconductor chip 9 and a transformer 140. In this case, the transmission side transmission convergence control part 120 and reception side transmission convergence control part 130 of the ATM controller 8 and the external PMD semiconductor chip 9 are connected by the serial transmission line of a 1-bit width, a FIFO memory 51a and the FIFO memory 52a for performing the data width conversion of 32/16 bits are provided inside a HOST/ DMAC connected to the card bus 6 and the processor 100 for the communication control is operated by clock signals 6a from the card bus 6.

3. 发明专利

JPH08274638A SIGNAL PROCESSING CIRCUIT AND GAIN ADJUSTMENT METHOD 失效
公开(公告)号：JPH08274638A
公开(公告)日：1996-10-18
申请号：JP7392495
申请日：1995-03-30
申请人： HITACHI LTD
发明人： NAGAI TOMOKAZU , ABE YOSHITAKA , YAMAKIDO KAZUO
IPC分类号： H03M1/00 , H03G3/00 , H03M1/18 , H04B1/40
摘要： PURPOSE: To reduce the production cost and to attain the highly accurate and two-way signal transmission gains for an A/D hybrid semiconductor integrated circuit which contains the A/D and D/A converters and performs two-way signal processing. CONSTITUTION: A return switch 116 is placed between the input of a sending amplifier 103 and the output of a receiving amplifier 114. A variable voltage source 117 is connected to the input of the amplifier 103 via a switch 120. Then a sending correction part 106 and a receiving correction part 111 are provided among the output of an A/D converter 105, the input of a D/A converter 112 and a signal processing part 107 respectively. These component parts are all controlled by an adjustment/control part 118, so that both sending and receiving gains are adjusted. As the gains are automatically adjusted while an LSI is operating, the gain trimming time is shortened and the number of trimming circuits is decreased for production of the LSI. Thus the LSI production cost can be reduced. Furthermore, the gain variance due to the temperature change caused in an LSI chip can be corrected by the highly accurate adjustment and then the gain stability is improved.

4. 发明专利

JPH01243725A OVER-SAMPLING A/D CONVERTER 失效
公开(公告)号：JPH01243725A
公开(公告)日：1989-09-28
申请号：JP6944788
申请日：1988-03-25
申请人： HITACHI LTD
发明人： YAMAKIDO KAZUO
IPC分类号： H03M3/02
摘要： PURPOSE:To economically realize an A/D converter for a broad band at high accuracy by cascade-connecting unit interpolating type A/D converters for plural stages. CONSTITUTION:Unit interpolating type A/D converters 1 and 2 at the same constitution are cascade-connected. In the A/D converter 1, an analog input signal detects an error voltage by a feedback signal from a local D/A converter 102 and a differential circuit 103, and adds an output to the error until a last sampled value by an analog integrating circuit 104. After the error is added again by an adder circuit 105, the output decides the polarity and the level of the error integral value by a voltage comparing circuit 106. A logical circuit 107 converts the output signal of the voltage comparing circuit 106 into the complement displaying signal of the converter 2. The output is applied through a digital integrating circuit 108 and the local D/A converter 102 to the differential circuit 103 as a comparative feedback signal. The input signal and output signal of the integrating circuit 108 and their arithmetic addition value are derived as the outputs.

5. 发明专利

JPH01222516A SWITCH CIRCUIT 失效
公开(公告)号：JPH01222516A
公开(公告)日：1989-09-05
申请号：JP4848288
申请日：1988-03-01
申请人： HITACHI LTD
发明人： YAMAKIDO KAZUO , SAKAGUCHI JIRO , MITOMO ISAMU , NAKAKOSHI ARATA
IPC分类号： H03K17/687
摘要： PURPOSE:To make the operation at a low power voltage stable by providing a capacitor to a gate of a 1st conductive transmission gate MOSFET provided between input and output terminals of an analog switch circuit and providing a 2nd conduction type MOSFET between the gate of the transmission gate MOSFET and the input terminal. CONSTITUTION:A capacitor CH receiving a control signal varied repetitively to a high or a low level at a prescribed period selectively at its other electrode is provided to the gate of the 1st conductive transmission gate MOSFETQ11 provided between an input terminal Si and an output terminal So of an analog switch circuit AS. Moreover, the 2nd conductive transmission gate MOSFETC1 receiving a control signal to its gate is provided between the gate of the trans mission MOSFETQ11 and the input terminal Si. Thus, when the control signal is given, a gate voltage having a level difference by nearly the power voltage periodically with respect to the input analog signal supplied to the gate of the transmission gate MOSFETQ11 to able to turn on the transmission gate MOSFETQ11 completely. Thus, the circuit is operated stably at a low power voltage.

6. 发明专利

JPH01155459A PROCESSOR AND PARALLEL COMPUTER 失效
公开(公告)号：JPH01155459A
公开(公告)日：1989-06-19
申请号：JP31401687
申请日：1987-12-14
申请人： HITACHI LTD
发明人： KAMEYAMA TATSUYA , YAMAKIDO KAZUO
IPC分类号： G06F15/16 , G06F9/38 , G06F15/177 , G06F15/80
摘要： PURPOSE:To lower a power cost by reducing power consumption and to miniaturize a computer by simplifying a cooling unit for heat generation by providing a means to detect the execution of a program and a power source current control means at an arithmetic processor. CONSTITUTION:The arithmetic processor 1 is constituted of independent blocks such as a program memory 2, an instruction decoding part 3 which decodes instructions read out sequentially from the memory 2, a data memory 4 operated according to sequence judged by the decoding part 3, an ALU5, and a multiplier 6, etc. Also, the decoding part 3 supplies the operating sequence of respective block, and also, supplies a power down control signal to perform the limitation of a power source current to power down circuits 9-1-9-4 attached on the block not being operated. And the circuits 9-1-9-4 limit the supply of the power source current to the block to which they belong, respectively. In such a way, it is possible to lower the power cost by reducing the power consumption, and to miniaturize the computer by simplifying the cooling unit for the heat generation.

7. 发明专利

JPS63232607A AMPLITUDE CONTROL DEVICE FOR PERIODICAL FUNCTION SIGNAL 失效
公开(公告)号：JPS63232607A
公开(公告)日：1988-09-28
申请号：JP6391387
申请日：1987-03-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMAMOTO TADATAKA , NISHIHARA TATSUYA , AKIYAMA HIROKI , YAMAKIDO KAZUO , MASUMURA ATSUO
IPC分类号： H03G3/00 , H03G3/02 , H04M15/00
摘要： PURPOSE:To improve the S/N by providing plural signal attenuation elements attenuating an analog periodical function signal level, a switch element selecting each signal attenuation element and a control means applying gradual increase/ decrease control to a prescribed phase of the analog periodical function signal in nearly ramp shape so as to miniaturize the circuit scale. CONSTITUTION:In instructing the output start of a sine wave signal to an up- down counter COUNT 1, switch control signals phi0-phin are brought into a high level in a form of pulse alternately in the order from all low levels to the phin-phi0. Switch elements SWn-SW0 are subject to switch control in order to control the amplitude of the sine wave signal Vin. Then, an output analog signal Vout increased gradually in nearly ramp shape of a stepwise shape is obtained at an output terminal of an inverting amplifier circuit 1 in the amplitude of the sine wave signal Vin. Thus, the production of overshoot and undershoot at the start and the end of the output sine wave signal Vout is prevented.

8. 发明专利

JPS6364410A PCM CODE DECODER HAVING DIGITAL BALANCING CIRCUIT 失效
公开(公告)号：JPS6364410A
公开(公告)日：1988-03-22
申请号：JP20786986
申请日：1986-09-05
申请人： HITACHI LTD
发明人： OZAKI NAOHIKO , YAMAKIDO KAZUO , MIYAKE NORIO , NISHIHARA TATSUYA
IPC分类号： H03M1/00 , H04B3/03 , H04B3/20
摘要： PURPOSE:To suppress echo signals by concatenating the first balancing circuit for characteristic correction of a part corresponding to A/D, D/A converter etc. and the second balancing circuit having chraracteristic of a part corresponding to outside part from a PCM code decoder, and inserting the first balancing circuit between A/D, D/A converters by a controlling instruction. CONSTITUTION:Analog input signals from a telephone set are A/D converted 8 through a pre-analog circuit 7 and change 9 sampling frequency and coding form and output four-line digital signals from a terminal 11. Digital received signals inputted from a terminal 12 are subjected to similar digital processing 9, D/A converted 14, and outputted 16 through a back-end analog circuit 5 and supplied to a telephone set. A balancing circuit 19 is made to cascade connection of a balancing circuit 19a that approximates only characteristic of A/D, D/A converters and a balancing circuit 16b that approximates characteristic of only the circuit between 16-6, and a switch 22 is controlled by signals from a terminal 23. Replica of echo signals 18 made in the balancing circuit 19 is added 20 and canceled. By this constitution, output of echo signals to the terminal 11 can be suppressed nicely.

9. 发明专利

JPS628050B2 失效
公开(公告)号：JPS628050B2
公开(公告)日：1987-02-20
申请号：JP15075080
申请日：1980-10-29
申请人： HITACHI LTD
发明人： SATO HIDEHIRO , YAMAKIDO KAZUO
IPC分类号： H03M1/66 , H03M1/38 , H03M1/80 , H04B14/04

10. 发明专利

JPS61239723A OVERSAMPLE TYPE D/A CONVERTER 失效
公开(公告)号：JPS61239723A
公开(公告)日：1986-10-25
申请号：JP8013185
申请日：1985-04-17
申请人： HITACHI LTD
发明人： KOKUBO MASARU , NISHIDA SHIGEO , YAMAKIDO KAZUO
IPC分类号： H03M1/08 , H03M1/00 , H03M3/02
摘要： PURPOSE:To prevent a gradient overload from being placed by varying the variation width of a feedback signal on the basis of the sum of the difference between the input signal and feedback signal of last sampling and the integration result of the difference as well as the reduction of quantization noises due to bit precision relaxation by utilizing a noise shaving method (of distributing the frequency component of quantization noises into high frequency areas). CONSTITUTION:The difference delta between a digital input signal composed of many oversampled bits and a digital feedback signal qa is obtained by an arithmetic circuit 1-1. The difference delta is integrated by an arithmetic circuit 1-2. Its output integral signal epsilon and difference delta are added together by an arithmetic circuit 1-3. Its sum output signal epsilon+delta is quantized by a comparing circuit 3 and applied to an arithmetic circuit 1-4, and the feedback signal qa is integrated and converted into a digital feedback signal qb by a D/A converter 4. The analog signal of the D/A converter is applied to a filter circuit 5 to remove higher harmonic signal components due to sampling. In a figure, 2-1 and 2-2 are registers.

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