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1. 发明专利

JP2012156740A Cdr circuit and receiving circuit 审中-公开
标题翻译： CDR电路和接收电路
公开(公告)号：JP2012156740A
公开(公告)日：2012-08-16
申请号：JP2011013604
申请日：2011-01-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAMANO DAISUKE , USUKINU TATSUNORI
IPC分类号： H04L7/02
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of realizing a CDR circuit, with a small area, of an interpolator method which requires no reference clock.SOLUTION: A CDR circuit 101 includes a data edge position measurement circuit 117 which measures the number of edges of the transmission data present close to and away from the edge of a reproduction clock, and a clock edge position measurement circuit 118 which measures the number of edges of the reproduction clock present close to and away from the edge of the transmission data. It also includes a frequency adjustment circuit 116 which adjusts frequency of the reproduction clock according to the measurement result of the data edge position measurement circuit 117 and the clock edge position measurement circuit 118. The discrimination of "close to edge" from "away from edge" is performed by controlling a minimum input amplitude of the CCL circuit.
摘要翻译：要解决的问题：提供一种能够实现不需要参考时钟的内插器方法的具有小面积的CDR电路的技术。解决方案：CDR电路101包括数据边缘位置测量电路117，其测量靠近和远离再现时钟边缘的发送数据的边缘数;以及时钟边缘位置测量电路118，其测量再现时钟的边缘数目靠近和远离传输数据的边缘。还包括根据数据边缘位置测量电路117和时钟边缘位置测量电路118的测量结果调整再现时钟的频率的频率调节电路116.从“远离边缘”的区分“接近边缘” “通过控制CCL电路的最小输入幅度来执行。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2011211318A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011211318A
公开(公告)日：2011-10-20
申请号：JP2010074762
申请日：2010-03-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUMOTO AKIRA , USUKINU TATSUNORI
IPC分类号： H03L7/099 , H03K3/354
CPC分类号： H03L7/087 , H03L7/0995
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which secures a phase margin by applying a digital compensation circuit advantageous in process migration in order to maintain characteristics while reducing the area of a phase locked loop circuit.SOLUTION: A digital compensation phase locked loop circuit 200 of the semiconductor device includes: a phase locked loop circuit 100 including a voltage controlled oscillator 104 having capacitors at oscillation nodes and consecutively controlled by an applied voltage; and a digital compensation circuit 201 which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator 104 in accordance with an input phase difference. A gain of the conventional voltage controlled oscillator 104, whose gain is determined by an applied voltage, is discretely changed by a control signal of the digital compensation circuit 201. The digital compensation circuit 201 dynamically controls the gain so as to secure the optimum phase margin, by applying a load to the oscillation node of the voltage controlled oscillator 104 with respect to a phase lead and decreasing the load with respect to a phase delay.
摘要翻译：要解决的问题：提供一种半导体器件，其通过应用在工艺迁移中有利的数字补偿电路来确保相位裕度，以便在减小锁相环电路的面积的同时保持特性。解决方案：数字补偿锁相环电路 200包括：锁相环电路100，其包括在振荡节点处具有电容器并由施加电压连续控制的压控振荡器104; 以及根据输入相位差可变地控制压控振荡器104的振荡节点处的电容器的数字补偿电路201。增益由施加电压决定的传统压控振荡器104的增益由数字补偿电路201的控制信号离散地改变。数字补偿电路201动态地控制增益，以确保最佳相位裕量通过相对于相位引线向压控振荡器104的振荡节点施加负载并相对于相位延迟减小负载。

3. 发明专利

JP2012156660A Receiving circuit, and semiconductor device and information processing system provided with the same 审中-公开
标题翻译：接收电路和半导体器件以及信息处理系统
公开(公告)号：JP2012156660A
公开(公告)日：2012-08-16
申请号：JP2011012475
申请日：2011-01-25
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： USHIO YUSHI , HAMANO DAISUKE , USUKINU TATSUNORI
IPC分类号： H03F3/68 , H03F3/34 , H03F3/45 , H04L25/02
CPC分类号： H04L25/0272 , H04L25/0292 , H04L25/03878
摘要： PROBLEM TO BE SOLVED: To provide a receiving circuit which amplifies a high-speed signal more than a low-speed signal and suppresses power consumption, and to provide a semiconductor device and an information processing system provided with the same.SOLUTION: The receiving circuit, and the semiconductor device and the information processing system provided with the same according to the present invention comprise a first amplifier and a second amplifier having a cutoff frequency lower than that of the first amplifier. A received signal is inputted to the first amplifier and the second amplifier, and an output of the second amplifier is subtracted from an output of the first amplifier to output a resultant signal.
摘要翻译：要解决的问题：提供一种接收电路，其高于低速信号放大高速信号并抑制功耗，并且提供一种具有该低电压信号的半导体器件和信息处理系统。解决方案：根据本发明的接收电路以及与其配备的接收电路及其信息处理系统包括具有比第一放大器的截止频率低的截止频率的第一放大器和第二放大器。接收到的信号被输入到第一放大器和第二放大器，并且从第一放大器的输出中减去第二放大器的输出，以输出结果信号。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2011147039A Phase and frequency comparator, and serial transmission device 有权
标题翻译：相位和频率比较器以及串行传输装置
公开(公告)号：JP2011147039A
公开(公告)日：2011-07-28
申请号：JP2010007693
申请日：2010-01-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： USUKINU TATSUNORI , ISEZAKI TSUYOSHI , KOYAMA TAKESHI
IPC分类号： H03L7/089 , H03K5/26 , H03L7/06
CPC分类号： H03D13/004
摘要： PROBLEM TO BE SOLVED: To provide a phase and frequency comparator for stabilizing loop bandwidth with a simple circuit. SOLUTION: This phase and frequency comparator which uses a reference clock 102 and a feedback clock 103 as inputs to output an up signal to a frequency synthesizer and a down signal to the frequency synthesizer is equipped with: a first phase and frequency comparison circuit 106; a second phase comparison circuit 107; and a delay circuit part 108 which uses the reference clock 102 and the feedback clock 103 as inputs and providing predetermined relative delay to the input of the first phase and frequency comparison circuit 106 and the input of the second phase comparison circuit 107. In the comparator, frequency comparison is performed by the first phase and frequency comparison circuit 106, and phase comparison is performed by the first phase and frequency comparison circuit 106 and the second phase comparison circuit 107 controlling a latch. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于通过简单电路稳定环路带宽的相位和频率比较器。解决方案：使用参考时钟102和反馈时钟103作为输入向频率合成器输出上行信号和向频率合成器输出降频信号的该相位和频率比较器装备有：第一相位和频率比较电路106; 第二相位比较电路107; 以及使用参考时钟102和反馈时钟103作为输入并向第一相位和频率比较电路106的输入和第二相位比较电路107的输入提供预定相对延迟的延迟电路部分108.在比较器，由第一相位和频率比较电路106执行频率比较，并且由第一相位和频率比较电路106以及控制锁存器的第二相位比较电路107执行相位比较。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2012151699A Latch circuit, cdr circuit, and receiving device 审中-公开
标题翻译：锁存电路，CDR电路和接收器件
公开(公告)号：JP2012151699A
公开(公告)日：2012-08-09
申请号：JP2011009362
申请日：2011-01-20
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAMANO DAISUKE , USUKINU TATSUNORI
IPC分类号： H03K3/356 , H03K3/0233 , H03K19/0175 , H03K19/0944 , H03L7/00 , H03L7/08 , H04L7/02
CPC分类号： H03K3/356139 , H03L7/0807 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To provide a receiving circuit in which power consumption is suppressed.SOLUTION: In the present invention, there is provided a circuit which, when a differential signal is differentially amplified, uses a pair of differential outputs to cut off a current generated by a differential input, thereby latching the differential signal. By application of the latch circuit, transmission data can be received even when a differential signal voltage difference of a received signal is small. Therefore, the number of amplifiers can be reduced to allow a reduction in power consumption of a receiving device.
摘要翻译：要解决的问题：提供抑制功耗的接收电路。解决方案：在本发明中，提供了一种电路，当差分信号被差分放大时，使用一对差分输出来截断由差分输入产生的电流，从而锁存差分信号。通过应用锁存电路，即使当接收信号的差分信号电压差小时，也可以接收发送数据。因此，可以减少放大器的数量以允许接收装置的功耗的降低。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2012054734A Phase synchronization circuit, cdr circuit, and reception circuit 有权
标题翻译：相位同步电路，CDR电路和接收电路
公开(公告)号：JP2012054734A
公开(公告)日：2012-03-15
申请号：JP2010195282
申请日：2010-09-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： USUKINU TATSUNORI , HAMANO DAISUKE
IPC分类号： H04L7/033 , H03K5/26 , H03K21/00 , H03K21/40 , H03L7/06 , H03L7/08 , H03L7/087
CPC分类号： H03L7/235 , H03L7/087
摘要： PROBLEM TO BE SOLVED: To provide a phase synchronization circuit capable of suppressing power consumption by lowering a frequency of a reference clock.SOLUTION: A frequency division clock having a phase difference corresponding to at least one cycle of a feedback clock is input into each of a first phase comparator and a second phase comparator for phase comparison with a reference clock. Based on a result of phase comparison between a received signal and the feedback clock, weighting of outputs of the first and the second phase comparators is performed for phase adjustment of the feedback clock by the weighted outputs.
摘要翻译：要解决的问题：提供一种能够通过降低参考时钟的频率来抑制功耗的相位同步电路。解决方案：具有对应于反馈时钟的至少一个周期的相位差的分频时钟被输入到第一相位比较器和第二相位比较器的每一个中，用于与参考时钟进行相位比较。基于接收信号和反馈时钟之间的相位比较的结果，执行第一和第二相位比较器的输出的加权，以通过加权输出对反馈时钟的相位调整。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2012253584A Cdr circuit, receiver, and transmission and reception system 审中-公开
标题翻译： CDR电路，接收器，传输和接收系统
公开(公告)号：JP2012253584A
公开(公告)日：2012-12-20
申请号：JP2011124790
申请日：2011-06-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAMANO DAISUKE , USUKINU TATSUNORI
IPC分类号： H04L7/02 , H03L7/08 , H03L7/085
CPC分类号： H04L7/0332 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/089 , H03L7/091
摘要： PROBLEM TO BE SOLVED: To improve phase follow-up accuracy of a CDR circuit using nonlinear phase comparator, receiver, and a reproduction clock of a transmission and reception system.SOLUTION: The CDR circuit 106, receiver 101, and transmission and reception system 100 applies weighting to an output of a nonlinear phase comparator into which reception data 105 and a reproduction clock 119 are input according to a delay or an advance of a clock with a phase difference of the reception data to the reproduction clock, and the phase of the reproduction clock is adjusted based on the weighted output.
摘要翻译：要解决的问题：使用非线性相位比较器，接收机和发送和接收系统的再现时钟来提高CDR电路的相位跟踪精度。解决方案：CDR电路106，接收机101和发送和接收系统100对非线性相位比较器的输出应用加权，根据延迟或前进，输入接收数据105和再现时钟119 具有接收数据与再现时钟的相位差的时钟，并且基于加权输出来调整再现时钟的相位。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2012253529A Cdr circuit 审中-公开
标题翻译： CDR电路
公开(公告)号：JP2012253529A
公开(公告)日：2012-12-20
申请号：JP2011123915
申请日：2011-06-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAMANO DAISUKE , USUKINU TATSUNORI
IPC分类号： H03K5/26 , H03L7/00 , H03L7/08 , H03L7/085
摘要： PROBLEM TO BE SOLVED: To provide a CDR circuit capable of eliminating use of an analog circuit in a charge pump or VCO and suppressing an increase in a circuit area, while using a linear phase comparator.SOLUTION: A phase comparator 902 detects an edge of transmission data with data edge detection circuits 111-114. Using data edge mask circuits 115-118, sampling circuits 119-122, low-pass filters 123-126 and analog-digital conversion circuits 127-130, a voltage of a reproduction clock is detected when the edge of the transmission data is detected and phase adjustment of the reproduction clock is implemented based on the detected voltage.
摘要翻译：要解决的问题：提供一种能够消除在电荷泵或VCO中使用模拟电路并抑制电路面积增加的CDR电路，同时使用线性相位比较器。解决方案：相位比较器902利用数据边缘检测电路111-114来检测发送数据的边缘。使用数据边缘掩码电路115-118，采样电路119-122，低通滤波器123-126和模拟数字转换电路127-130，当检测到发送数据的边缘时，检测再现时钟的电压，基于检测到的电压来实现再现时钟的相位调整。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2007041978A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007041978A
公开(公告)日：2007-02-15
申请号：JP2005227376
申请日：2005-08-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： USUKINU TATSUNORI , SUZUKI KAZUHISA , TSUGE MASATOSHI
IPC分类号： G06F13/42 , H03L7/199
CPC分类号： H03M9/00 , G06F1/24
摘要： PROBLEM TO BE SOLVED: To reduce circuit scale and power consumption by facilitating timing design for simultaneous interrupt handling between a plurality of circuit blocks of high speed operation. SOLUTION: A semiconductor device has a clock signal generation circuit 5, and the plurality of circuit blocks 6 operated in synchronism with a clock signal clk. The plurality of circuit blocks are each reset on receiving an interrupt signal reset_in output in synchronism with the clock signal in a frequency locking process. A timing margin is thus significantly improved. COPYRIGHT: (C)2007,JPO&INPIT

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